A bipolar 32b processor chip

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156966

F. Buckley, S. Chen, J. Hilse, M. Homan, G. Machol, L. Pereira, J. Terry, G. Watanabe

引用次数: 2

Abstract

The architecture, circuitry, packaging and design of a 14×16mm 32b CPU chip dissipating 16W will be described. The chip, which has been built in a 2μm bipolar process with 8-level cascode ECL circuitry, executes a mainframe instruction set.

查看原文本刊更多论文

双极32b处理器芯片

本文将描述功耗为16W的14×16mm 32b CPU芯片的架构、电路、封装和设计。该芯片采用2μm双极工艺，采用8级级联码ECL电路，执行大型机指令集。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量