1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"An experimental 4Mb CMOS DRAM","authors":"T. Furuyama, T. Ohsawa, Y. Watanabe, H. Ishiuchi, T. Tanaka, K. Ohuchi, H. Tango, K. Natori, O. Ozawa","doi":"10.1109/ISSCC.1986.1157013","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157013","url":null,"abstract":"technology developments were performed, in addition to the use of previously-established technologies, some of which have been demonstrated for 1 M CMOS DRAMs”~. The RAM was fabricated in a twintub CMOS process with 1 . 0 ~ design rules, which are affordable minimum limits for VLSIs obtained by present aligners. The array consists of trenched, N-channel, depletion-type capacitor cells in a P-well, which helps to reduce soft error rate314. Figure 1 shows a cross-sectional SEM microphotograph of the cell. Cell storage capacitance is 40fF with a 31-1 deep trench. Even though they are not necessari1y needed for Vcc/2 for precharged bitlines, dummy cells having a full memory cell capacitance and Vcc /2 level are adopted making the sense amplifiers less susceptible to bitline precharge level variations. Memory cell, dummy cell, and sense amplifier circuitry are shown in Figure 2. Considering a transition from llrl to 4M, many problems become more serious. One of these problems is operating current. The RAM is divided into eight 512K blocks. Together with Vcc/2 bitline precharge, one fourth of the blocks is activated during each RAS operating cycle to reduce power dissipation due to bitline discharge. However, the active current and especially the peak current are still not small enough to neglect since these are causes of V c c and VSS noise. Thus, an exclusive power supply wiring technique for sense amplifiers is applied to avoid the effect of bitline discharge and reduce current noise in peripheral circuit operation. Since memory test time markedly increases with memory size, the RAM has an 8b parallel test mode operation which suppresses the RAM test time. This mode is available for both x1 and x4 packaged device testing as well as for die sort testing. The test mode is activated by applying a high voltage to an extra TEN (test enable) pad. To obtain a high quality 4M DRAM, several new circuit and process","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114116145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 32b CMOS VLSI microprocessor with on-chip virtual memory management","authors":"Y. Yano, J. Iwasaki, Y. Sato, T. Iwata, K. Nakagawa, M. Ueda","doi":"10.1109/ISSCC.1986.1156924","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156924","url":null,"abstract":"mented by using a double-metal layer CMOS process technology with 1.5pm design rule to integrate 375,000 transistors on a single-chip. It operates at 16MHz, and consumes 1.5\". The processor has six independently-operational function-units that form a pipeline structure, as shown in Figures 2 and 3. The PFU (Prefetch Unit) prefetches instructions into a 16-byte prefetch queue. The IDU (Instruction Decode Unit) decodes the instructions, and sets commands into a two words by 53b decoded instruction queue (IDQ). The EAG (Effective Address Generator) calculates the operand address, while the MMU (Memory Management Unit) translates virtual address into real address. A BCU (Bus Control Unit) initiates memory access for instruction/data fetch. The EXL (Execution Unit) carries out the instruction-set function. The integrated memory management unit (MMU) has a 16-entry full associative Translation Look-aside Buffer (TLB) and a protection check circuitry. The TLB holds sixteen virtual-to-real address pairs in full associative manner, each consists of a 21b contents addressable memory (CAM) for virtual address tag and a 28b data memory for real address. The TLB can translate the virtual address to real address in 36ns in worst case. The chip microphotograph is shown in Figure 1. It has been imple-","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131789015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 32b single-chip microprocessor","authors":"S. Ong, H. Chao, M. Tsai, F. Shih, J. C. L. Hou, K. Lewis, J. Tang, C. A. Trempel, R. Hadsel, H. Yu, P. McCormick, C. Davis, A. L. Diamond, T. J. Medve, J. Higham","doi":"10.1109/ISSCC.1986.1156969","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156969","url":null,"abstract":"This paper will present a 32b single-chip microprocessor implementing 102 mainframe instructions and supporting the emulation of the rest of the instructions. The chip, 10mm × 10mm with 200,000 transistor sites, is designed for 10MHZ worst case and operates at 16MHZ with 3W dissipation.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134396089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2V amplitude-linear phase-locked loop","authors":"M. Wilcox","doi":"10.1109/ISSCC.1986.1156881","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156881","url":null,"abstract":"A phase-locked loop IC using a sampled-data amplitude-linear phase detector, will be covered. The CMOS circuit operates over a 2.9V range and performs FM demodulation up to 500kHz.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133872644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3.5ns, 2W, 20mm216Kb ECL bipolar RAM","authors":"K. Yamaguchi, H. Nambu, K. Kanetani, N. Homma, Y. Nishioka, A. Uchida, K. Ogiue","doi":"10.1109/ISSCC.1986.1156927","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156927","url":null,"abstract":"THIS PAPER WILL DESCRIBE a 3.5ns ECL 16Kb bipolar RAM with a power dissipation of 2W, cell size of 4 9 5 ~ 2 and chip size of 20mm2. The most critical requirements for bipolar RAMs are high speed, low power dissipation and small chip size. Two circuit techniques are proposed to meet the foregoing criteria: ( I ) a Schottky barrier diode (SBD) decoder combined with an address buffer and a latch circuit having three-level VBB; ( 2 ) a Darlington word driver having double-stage discharge circuits. The SBD decoder circuit combined with the address buffer and latch circuits is shown in Figure 1. The decoder reduces access time by 20% compared to a conventional multi-emitter decoder, because the parasitic capacitance CDE at the decoder output can be reduced by about 65%. The lower capacitance is due to the small area and small junction capacitance per unit area. Two SBDs have been connected in series to obtain a forward voltage higher than a base-emitter voltage VBE of the transistor QE. This enables the decoder to be completely cut off, insuring a sufficiently high level at the decoder output. To realize even higher speeds at the system level, an on-chip buffer and latch must be combined with the SBD decoder. However, a simple combination of the conventional address buffer and latch using a series gate’ and SBD decoder cannot be used because of transistor (Ql /Q2) saturation under a given supply voltage (-5.2V); Figure 1. To overcome this problem, an address buffer and latch with a threelevel VBB, also shown in Figure 1, is proposed. The latch operation can be performed by the three-level VBB without any loss in speed. Until the clock CLK turns on, the VBB generator offers a VBB in accordance with the previous address input (ADR) levels as shown in Figure 2. That is, the VBB is set to a lower (higher) level than any address input level for high (low) level address input. Therefore, the outputs of the address buffer are held high or low regardless of the following address input changes. When the clock CLK turns on at to, the output of the VBB generator is switched to a standard VBB level for a 10K or lOOK logic family. Thus, the outputs of the address buffers can be changed in accordance with the address inputs. This address information is retained when the CLK turns off again. Figure 3 shows a Darlington word driver using double-stage discharge circuits connected to each of the transistor emitters. Sufficient discharge currents are provided (I1 = 2mA, I2 = 6mA) without a significant voltage drop on the word line. Conventional delayed discharge circuits are also used at the end of the word lines to increase the cell margin. Since both discharge circuits are delay-type, it is possible to maintain a high current after the word line voltage switches to a low level. The driver reduces further the access time by about 15Yc. The increase in power dissipation is negligibly small in spite of the high","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133791468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 70ns 2Mb mask ROM with a programmed memory cell","authors":"S. Ariizumi, T. Iwase, M. Takizawa, T. Mocozuki, M. Ono, K. Maeda, M. Asano, F. Masuoka","doi":"10.1109/ISSCC.1986.1156970","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156970","url":null,"abstract":"This report will cover the development of a 70ns 2Mb CMOS mask ROM with a through-hole programmed memory, using double-poly layers and self-aligned contact. With 1.5μm design rules, the die measures 6.57 × 11.9mm.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CMOS erasable programmable logic with zero standby power","authors":"Sau C. Wong, H. So, C. Hung, J. Ou","doi":"10.1109/ISSCC.1986.1156900","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156900","url":null,"abstract":"Programmable logic ICs with a complexity of up to 2000 gates will be reported. An input transition detector powers up the circuits and differential logic in the critical speed paths affords a 25ns delay.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134308964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 35ns 128K fusible bipolar PROM","authors":"Phi Thai, S. Chang, Mann Yang","doi":"10.1109/ISSCC.1986.1156972","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156972","url":null,"abstract":"A bipolar PROM using 2μm slot-isolation technology will be reported. Circuits include a column-current multiplexer and temperature-compensated sensing. The die size is 306×224 mil2.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121861360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 30ns 256K full CMOS SRAM","authors":"N. Okazaki, F. Miyaji, K. Kobayashi, Y. Harada, J. Aoyama, T. Shimada","doi":"10.1109/ISSCC.1986.1156880","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156880","url":null,"abstract":"This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm× 13.2μm.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125706927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implantable multielectrode array with on-chip signal processing","authors":"K. Najafi, K. Wise","doi":"10.1109/ISSCC.1986.1157002","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157002","url":null,"abstract":"A 20-channel microelectrode array used to sense meural signals will be described. An implantable device, it incorporates on-chip signal processing, self-testing, and consumes 5mW from a single 5V supply. The chip, with a 1.3mm2area, has 6μm features.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123930339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}