1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

{"title":"A 1.5Mb/s × 128-channel time switch LSI for digital still pictures","authors":"T. Nikaido, S. Yamada, H. Fukada, S. Suzuki","doi":"10.1109/ISSCC.1986.1156945","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156945","url":null,"abstract":"This paper will report on a 128-channel time switch for conversion of digital picture format. The chip operates at a 224Mbs/s throughput with a 56MHz clock. It contains 54,000 transistors in an area of 6.7,2mm2using 2.5μm CMOS and dissipates 1.5W.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"744 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 13ns/500mW 64Kb ECL RAM","authors":"K. Ogiue, M. Odaka, S. Miyaoka, I. Masuda, T. Ikeda, K. Tonomura, T. Ohba","doi":"10.1109/ISSCC.1986.1156897","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156897","url":null,"abstract":"This paper will cover the design of a 16K×4 SRAM which uses buried twin-well 2μm CMOS transistors and 4GHz cutoff frequency bipolar transistors. The circuit combines a high-resistance polysilicon - load NMOS memory cell with mixed MOS/bipolar periphery circuits to achieve ECL compatibility, 13ns access times and an operating power of 500mW at 40MHz.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 32b digital signal processor for motor control","authors":"J. Santos, J. Costello, D. Squires, J. Kmetz, R. Davis","doi":"10.1109/ISSCC.1986.1156995","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156995","url":null,"abstract":"This paper will describe a 32b digital signal processor with 0.5 to 1.5μs instruction cycle times for motor position control, A 4.04×4.83mm2chip containing 25,000 transistors has been made in 3μm NMOS technology and dissipates 250mW.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124339987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formal opening of conference / keynote address","authors":"A. Grebene","doi":"10.1109/ISSCC.1986.1156905","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156905","url":null,"abstract":"","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126255817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1Mb virtually SRAM","authors":"T. Sakurai, K. Sawada, K. Nogami, T. Wada, M. Isobe, M. Kakumu, S. Morita, S. Yokogawa, M. Kinugawa, T. Asami, K. Hashimoto, J. Matsunaga, H. Nozawa, T. Iizuka","doi":"10.1109/ISSCC.1986.1156930","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156930","url":null,"abstract":"Suppressed VLSI with Submicron Geometry”, ISSCC DIGEST ’Sakurai, T., Kakumu, M . and Iizuka, T., “Hot-Carrier O F T E C H N I C A L P A P E R S , p. 272-273; Feb., 1985. “HotJ S S C ; to he published. Carrier Generation in Submicron VLSI Environment”, IEEE Insertion (NOEMI) technology5 is applied selectively to bootstraped nodes to endow hot-carrier resistancy to the circuits. N-channel memory cells are embedded in a P-well for protection from the minority carrier injection from I/O pins and alpha-particle induced electrons. Yo substrate bias is applied to reduce the standby current. Process related parameters are listed in Table 1. A double-level poly-Si and double level A1 process has been employed for circuit speed. The cell capacitor is planar and the design rule is 1.2pm. A microphotograph of the chip is shown in Figure 4. Figure 5 demonstrates a typical address access time of 62ns. The slower access is the worst case access time; Le., refresh operation taking place in advance of the normal access. The faster access is without refresh. This measurement is carried out by a test enable pin that affords control of the refresh-request signal externally. Since the access time without refresh is 48ns, the access time overhead by the background refresh is 29%. Electron beam tested internal waveforms are also shown in Figure 5. Quick switch from refresh to normal operation can be achieved by the dual bootstrap system, where one system is precharged when the other one is in operation. The pin configuration is shown in Figure 6. SRAMs. The SRAM is believed to be a promising substitute for large-capacity Acknowledgments The authors wish to thank S. Fujii, S. Saito, K. Natori, T. Ohtani, K. Taniguchi, Y. Nishi and K. Shimuzu for encouragement and discussions. Theyalso thank Y. Ito, K. Sat0 and K. Matsuda for support. Technology Twin well CMOS Layers Double poly-Si and double A1 Gate length l .op(NMOS), 1.2puPMOS) Junction depth 0.20,u(N+), 0.35p(Pt) Cap. oxide thickness l0nm Gate oxide thickn ss 20nm Poly-Si (WidthlSpace) 1.0pm / 1.4pm 1 s t AI (WidthlSpace) 1.3pm / 1.5pm Contact hole 1.lpm / 1.4pm 2nd Al (WidthlSpace) 1.8pm / 1.9pm Via hole 1.8pm / 2.0pm TABLE 1-Process parameters.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131907958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Competing technologies for ultrahigh-speed SRAMs and their applications","authors":"F. Lee","doi":"10.1109/ISSCC.1986.1156934","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156934","url":null,"abstract":"Advanced MOS and bipolar technologies, using1-2μm lithography, have increased dramatically the complexity of 16K to 256K SRAMs and reduced access time to 3 to 30ns, respectively. Meanwhile, GaAs technology has produced 1 to 3ns, and 1K to 4K SRAMs. The present status and the future projections of these competing technologies will be discussed. The user's point-of-view assessing implementation of high speed SRAMS in a system environment will be offered.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"50 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120919463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A full duplex analog front-end chip set for split-band and echo-canceling modems","authors":"J. Bertails, C. Perrin, L. Tallaron, L. Mary, C. Delange","doi":"10.1109/ISSCC.1986.1156878","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156878","url":null,"abstract":"This paper will report on an analog CMOS three-chip set which interfaces to an associated modem digital-signal processor. The chip set performs A/D and D/A conversion, analog subtraction of replicated echo signal, filtering, automatic gain control, and analog carrier detection for split-band modems up to 2400b/s and echo-canceling modems up to 16,800b/s. Implementation was in 4μ CMOS.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129863065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 16ns CMOS EEPLA with reprogrammable architecture","authors":"D. Rutledge, J. Turner, R. Darling, G. Josephson","doi":"10.1109/ISSCC.1986.1156977","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156977","url":null,"abstract":"A PLA, whose architecture may be electrically programmed, will be described. The device has been built in 1.2μm EEPROM technology and operates at 20MHz with 380mW dissipation. On-chip scan diagnostics are used for testing.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129581596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CML compatible GaAs gate array","authors":"H. Hirayama, T. Furutsuka, Y. Tanaka, M. Kaga, M. Kanamori, K. Takahashi, H. Kohzu, A. Higashisaka","doi":"10.1109/ISSCC.1986.1157018","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157018","url":null,"abstract":"This paper will describe a CML compatible GaAs 3K array using buffered FET logic. Propagation delays of 59ps and 186ps per gate were achieved for load conditions of 65μm and 2mm line lengths, respectively. 32b shift register operation at 1.2 GHz clock rates was verified.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132885330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CMOS electrically reprogrammable ASIC with multi-level random logic capabilities","authors":"E. Goetting, S. Revak, Z. Jan","doi":"10.1109/ISSCC.1986.1156901","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156901","url":null,"abstract":"A 24-pin electrically-reprogrammable ASIC, implemented in CMOS EEPROM technology with two-layer polysilicon and two-layer metal, providing user logic complexity of 600-800 gate equivalents, will be described. Speeds of 15ns per internal logic level have been obtained with 50mW consumption.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"149 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113985776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}