具有多层随机逻辑能力的CMOS电可编程ASIC

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156901

E. Goetting, S. Revak, Z. Jan

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引用次数: 0

摘要

将描述一种24针电可编程ASIC，采用两层多晶硅和两层金属的CMOS EEPROM技术实现，提供600-800栅极等效的用户逻辑复杂性。以50mW的消耗获得了每个内部逻辑级15ns的速度。

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A CMOS electrically reprogrammable ASIC with multi-level random logic capabilities

A 24-pin electrically-reprogrammable ASIC, implemented in CMOS EEPROM technology with two-layer polysilicon and two-layer metal, providing user logic complexity of 600-800 gate equivalents, will be described. Speeds of 15ns per internal logic level have been obtained with 50mW consumption.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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