A CML compatible GaAs gate array

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1157018

H. Hirayama, T. Furutsuka, Y. Tanaka, M. Kaga, M. Kanamori, K. Takahashi, H. Kohzu, A. Higashisaka

引用次数: 11

Abstract

This paper will describe a CML compatible GaAs 3K array using buffered FET logic. Propagation delays of 59ps and 186ps per gate were achieved for load conditions of 65μm and 2mm line lengths, respectively. 32b shift register operation at 1.2 GHz clock rates was verified.

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兼容CML的砷化镓栅极阵列

本文将描述一个使用缓冲场效应晶体管逻辑的CML兼容GaAs 3K阵列。在线路长度为65μm和2mm的负载条件下，每个栅极的传输延迟分别为59ps和186ps。验证了在1.2 GHz时钟速率下的32b移位寄存器操作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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