A 16ns CMOS EEPLA with reprogrammable architecture

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156977

D. Rutledge, J. Turner, R. Darling, G. Josephson

引用次数: 3

Abstract

A PLA, whose architecture may be electrically programmed, will be described. The device has been built in 1.2μm EEPROM technology and operates at 20MHz with 380mW dissipation. On-chip scan diagnostics are used for testing.

查看原文本刊更多论文

具有可重新编程结构的16ns CMOS EEPLA

本文将描述一个PLA，其结构可以通过电气编程实现。该器件采用1.2μm EEPROM技术，工作频率为20MHz，功耗为380mW。片上扫描诊断用于测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量