A 1Mb virtually SRAM

Suppressed VLSI with Submicron Geometry”, ISSCC DIGEST ’Sakurai, T., Kakumu, M . and Iizuka, T., “Hot-Carrier O F T E C H N I C A L P A P E R S , p. 272-273; Feb., 1985. “HotJ S S C ; to he published. Carrier Generation in Submicron VLSI Environment”, IEEE Insertion (NOEMI) technology5 is applied selectively to bootstraped nodes to endow hot-carrier resistancy to the circuits. N-channel memory cells are embedded in a P-well for protection from the minority carrier injection from I/O pins and alpha-particle induced electrons. Yo substrate bias is applied to reduce the standby current. Process related parameters are listed in Table 1. A double-level poly-Si and double level A1 process has been employed for circuit speed. The cell capacitor is planar and the design rule is 1.2pm. A microphotograph of the chip is shown in Figure 4. Figure 5 demonstrates a typical address access time of 62ns. The slower access is the worst case access time; Le., refresh operation taking place in advance of the normal access. The faster access is without refresh. This measurement is carried out by a test enable pin that affords control of the refresh-request signal externally. Since the access time without refresh is 48ns, the access time overhead by the background refresh is 29%. Electron beam tested internal waveforms are also shown in Figure 5. Quick switch from refresh to normal operation can be achieved by the dual bootstrap system, where one system is precharged when the other one is in operation. The pin configuration is shown in Figure 6. SRAMs. The SRAM is believed to be a promising substitute for large-capacity Acknowledgments The authors wish to thank S. Fujii, S. Saito, K. Natori, T. Ohtani, K. Taniguchi, Y. Nishi and K. Shimuzu for encouragement and discussions. Theyalso thank Y. Ito, K. Sat0 and K. Matsuda for support. Technology Twin well CMOS Layers Double poly-Si and double A1 Gate length l .op(NMOS), 1.2puPMOS) Junction depth 0.20,u(N+), 0.35p(Pt) Cap. oxide thickness l0nm Gate oxide thickn ss 20nm Poly-Si (WidthlSpace) 1.0pm / 1.4pm 1 s t AI (WidthlSpace) 1.3pm / 1.5pm Contact hole 1.lpm / 1.4pm 2nd Al (WidthlSpace) 1.8pm / 1.9pm Via hole 1.8pm / 2.0pm TABLE 1-Process parameters.