A 32b CMOS VLSI microprocessor with on-chip virtual memory management

mented by using a double-metal layer CMOS process technology with 1.5pm design rule to integrate 375,000 transistors on a single-chip. It operates at 16MHz, and consumes 1.5". The processor has six independently-operational function-units that form a pipeline structure, as shown in Figures 2 and 3. The PFU (Prefetch Unit) prefetches instructions into a 16-byte prefetch queue. The IDU (Instruction Decode Unit) decodes the instructions, and sets commands into a two words by 53b decoded instruction queue (IDQ). The EAG (Effective Address Generator) calculates the operand address, while the MMU (Memory Management Unit) translates virtual address into real address. A BCU (Bus Control Unit) initiates memory access for instruction/data fetch. The EXL (Execution Unit) carries out the instruction-set function. The integrated memory management unit (MMU) has a 16-entry full associative Translation Look-aside Buffer (TLB) and a protection check circuitry. The TLB holds sixteen virtual-to-real address pairs in full associative manner, each consists of a 21b contents addressable memory (CAM) for virtual address tag and a 28b data memory for real address. The TLB can translate the virtual address to real address in 36ns in worst case. The chip microphotograph is shown in Figure 1. It has been imple-