30ns 256K全CMOS SRAM

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156880

N. Okazaki, F. Miyaji, K. Kobayashi, Y. Harada, J. Aoyama, T. Shimada

{"title":"30ns 256K全CMOS SRAM","authors":"N. Okazaki, F. Miyaji, K. Kobayashi, Y. Harada, J. Aoyama, T. Shimada","doi":"10.1109/ISSCC.1986.1156880","DOIUrl":null,"url":null,"abstract":"This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm× 13.2μm.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 30ns 256K full CMOS SRAM\",\"authors\":\"N. Okazaki, F. Miyaji, K. Kobayashi, Y. Harada, J. Aoyama, T. Shimada\",\"doi\":\"10.1109/ISSCC.1986.1156880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm× 13.2μm.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1156880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文将介绍一种采用单聚双金属p阱CMOS制造的具有分隔字线的32K×8全CMOS SRAM，其地址访问时间为30ns。待机功耗500mW。CMO5存储单元的尺寸为10.6μ mx13.2 μm，采用6个晶体管，布局规则为1.0μm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 30ns 256K full CMOS SRAM

This paper will cover a 32K×8 full CMOS SRAM with a divided word line that has been fabricated in single-poly, double-metal, P-well CMOS, Address access time is 30ns. Standby power dissipation is 500mW. The CMO5 memory cell using 6 transistors, designed in 1.0μm layout rules, measures 10.6μm× 13.2μm.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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