零待机功率的CMOS可擦除可编程逻辑

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156900

Sau C. Wong, H. So, C. Hung, J. Ou

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引用次数: 7

摘要

可编程逻辑ic的复杂性高达2000门将被报道。输入跃迁检测器为电路供电，关键速度路径中的差分逻辑提供25ns延迟。

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CMOS erasable programmable logic with zero standby power

Programmable logic ICs with a complexity of up to 2000 gates will be reported. An input transition detector powers up the circuits and differential logic in the critical speed paths affords a 25ns delay.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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