A 19ns 250mW programmable logic device

Abstract

FAST PROGRAMMABLE LOGIC DEVICES are traditionally implemented in the bipolar fuse technology. Bipolar fuse technology satisfies the speed requirement of these devices, but has two major disadvantages: ( I ) significantly higher power consumption and, (2) fuse technology does not allow reprogrammability and 100% testability. High-speed CMOS technology along with the demonstrated reliability and reprogrammability of FAMOS devices is gaining momentum in high-speed programmable logic design. A 19ns, low-power 250mW, 44-input term and 132 product term programmable logic device using 1 . 2 ~ N-well CMOS EPROM technology will be described. The power is one fourth of equivalent bipolar parts. Both the N and P channel peripheral transistors use self-aligned, shallow-junction, lightlydoped drains (LDD). The LDD structure reduces overlap capacitance and minimizes hot electron injection. The programmable element is a two-transistor FAMOS cell optimized for speed and programmability; Figure 1. The cell size is 133p2. The programming characteristic is shown in Figure 2. The technology uses a back bias generator, which reduces the parasitic capacitance, improves field threshold for better programming and provides latch up immunity greater than 200mA. The die size is 3.lmm x 4.lmm; Figure 3. Typical propagation delay of 19ns and clock to output of lOns