A 1Mb DRAM with 33MHz serial I/O ports

THIS PAPER WILL DESCRIBE a 1Mb image memory, 256k x 4 DRAM with 30ns bit rate serial 1/0 ports with special features for TV or VCR image display applications. In this development, 4b wide data are shifted into 4 sets of 8 b shift registers, loaded from the DRAM to other 4 sets of 8b shift registers and shifted out through serial ports. These operations are performed under 33MHz clock without any idle time. One field of a color TV signal has 256k x 8b, so that only two chips of this memory are enough to store it. A block diagram of the memory is shown in Figure 1. The DRAM block is constructed with 512 rows and 2,048 columns. 2,048 columns are divided into 4 groups, and each group has 64 x 8b columns. Serial data handling block is constructed with four sets of 8 I/O selectors, 8b serialin and serial-out registers. Figure 2 shows the timing diagram of this memory. In the write cycle, input data are shifted into an 8 b serial-in register by synchronizing the rising edge ofSIC clock through data input pins, D l 1 to D14. At the falling edge of WS clock, 32b data in four 8b serial-in re&ers are transfered to 32b data registers. And at the falling edge of WE clock, 32b data go through I/O selectors and to 32b memory cells which have been selected and activated by IS &dress pins (A0 A14), a chip select pin (CS), and a chip enable pin (CE). In the read mode, readout data from the selected address are sensed, go through I/O selectors and are loaded on four 8b serial out registers at the falling edge of RS clock. Data from the serial out registers are shifted out serially at every rising edge of SOC clock through data