J. Neal, B. Holland, S. Inoue, W. Loh, H. McAdams, Kenneth A. Poteet
{"title":"具有专为测试而设计功能的1Mb CMOS DRAM","authors":"J. Neal, B. Holland, S. Inoue, W. Loh, H. McAdams, Kenneth A. Poteet","doi":"10.1109/ISSCC.1986.1156947","DOIUrl":null,"url":null,"abstract":"A mask programmable 1Mb CMOS DRAM family has been developed featuring design-for-test functions which allow the memory to reconfigured as an 8b parallel 128Kb organization to reduce test time. With a 1μm twin-well CMOS technology and a contactless trench cell, the chip measures 49mm2.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"A 1Mb CMOS DRAM with design-for-test functions\",\"authors\":\"J. Neal, B. Holland, S. Inoue, W. Loh, H. McAdams, Kenneth A. Poteet\",\"doi\":\"10.1109/ISSCC.1986.1156947\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A mask programmable 1Mb CMOS DRAM family has been developed featuring design-for-test functions which allow the memory to reconfigured as an 8b parallel 128Kb organization to reduce test time. With a 1μm twin-well CMOS technology and a contactless trench cell, the chip measures 49mm2.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1156947\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A mask programmable 1Mb CMOS DRAM family has been developed featuring design-for-test functions which allow the memory to reconfigured as an 8b parallel 128Kb organization to reduce test time. With a 1μm twin-well CMOS technology and a contactless trench cell, the chip measures 49mm2.