{"title":"混合硅晶圆级封装技术","authors":"R. Johnson, J. Davidson, R. Jaeger, D. Kerns","doi":"10.1109/ISSCC.1986.1156981","DOIUrl":null,"url":null,"abstract":"Procedures developed for mounting ICs in holes in a silicon wafer and inter-connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Hybrid silicon wafer-scale packaging technology\",\"authors\":\"R. Johnson, J. Davidson, R. Jaeger, D. Kerns\",\"doi\":\"10.1109/ISSCC.1986.1156981\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Procedures developed for mounting ICs in holes in a silicon wafer and inter-connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1156981\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Procedures developed for mounting ICs in holes in a silicon wafer and inter-connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.