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Digest of Papers. 1992 IEEE VLSI Test Symposium最新文献

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Probe point insertion for at-speed test 用于高速测试的探针点插入
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232756
E. Rudnick, V. Chickermane, J. Patel
{"title":"Probe point insertion for at-speed test","authors":"E. Rudnick, V. Chickermane, J. Patel","doi":"10.1109/VTEST.1992.232756","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232756","url":null,"abstract":"Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan, or silicon-based solutions like Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed. In this paper, a design-for-test method which permits at-speed testing is introduced. The method is based on probe point insertion for improved observability. Improvements in fault coverage were made for all 16 of the ISCAS-80 benchmark circuits studied. Fault coverages between 99% and 100% were obtained for six circuits, and 100% ATG efficiency achieved on all but two circuits.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128051058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A new tool for random testability evaluation using simulation and formal proof 一种基于模拟和形式化证明的随机测试性评估新工具
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232773
E. Simeu, Anura Puissochet, J. Rainard, Anne-Marie Tagant, M. Poize
{"title":"A new tool for random testability evaluation using simulation and formal proof","authors":"E. Simeu, Anura Puissochet, J. Rainard, Anne-Marie Tagant, M. Poize","doi":"10.1109/VTEST.1992.232773","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232773","url":null,"abstract":"A set of tools is described, allowing one to compute random testability measurement for combinational circuits, based on a black box worst case hypothesis. These tools provide enough information to allow circuit modification, in order to meet a prescribed testability value. The efficiency of these tools is due to the use of a statistical method combined with formal proof mechanisms. The random testability of the complete ISCAS benchmark of combinational circuits is computed. For the least testable circuits, a few modifications, guided by the testability measurements, are shown to be sufficient to make them randomly testable.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133277738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The split boundary scan register technique for testing board interconnects 测试电路板互连的分割边界扫描寄存器技术
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232722
N. Haider, N. Kanopoulos
{"title":"The split boundary scan register technique for testing board interconnects","authors":"N. Haider, N. Kanopoulos","doi":"10.1109/VTEST.1992.232722","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232722","url":null,"abstract":"Presents a new approach to testing board interconnects, on a board containing three-state nets and with chips equipped with the boundary scan architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, the authors have concentrated on the walking 1's and 0's for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of walking 1/0 in linear time.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133380156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Built-in self-diagnostic by space-time compression of test responses 内置自诊断的时空压缩测试响应
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232740
M. Karpovsky, S. M. Chaudhry
{"title":"Built-in self-diagnostic by space-time compression of test responses","authors":"M. Karpovsky, S. M. Chaudhry","doi":"10.1109/VTEST.1992.232740","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232740","url":null,"abstract":"Presents two different methodologies for built-in self-diagnostic of boards and systems by space-time compression of test responses. The first method, soft decision, uses nonbinary multiple error-correcting codes to obtain space-time signatures. These obtained signatures and the corresponding precomputed references are compared and magnitudes of distortions in signatures are analyzed to identify faulty components. The second method, hard decision, makes use of the information indicating whether the corresponding signatures are distorted or not. Both approaches show considerable savings in hardware overheads when compared with a straightforward approach where a separate signature is required for every component. A transition from the soft to hard decision approach results in an increase in the number of signatures required for diagnostic but at the same time it results in a decrease in the complexity of a fault locating algorithm. Results pertaining to VLSI implementations are presented where the hardware overhead is estimated in terms of two-input equivalent gates.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122031908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Techniques to increase sequential ATPG performance 提高连续ATPG性能的技术
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232762
E. Macii, A. Meo
{"title":"Techniques to increase sequential ATPG performance","authors":"E. Macii, A. Meo","doi":"10.1109/VTEST.1992.232762","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232762","url":null,"abstract":"An automatic test pattern generation (ATPG) system for sequential circuits is described. Techniques such as testability measures, 9-valued functions, incompatibility function and fault simulation have been added to the basic algorithm in order to increase the fault coverage and reduce the test generation time. The entire ATPG system has been benchmarked on the set of ISCAS89 circuits.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127055046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On fault deletion problem in concurrent fault simulation for synchronous sequential circuits 同步时序电路并发故障仿真中的故障删除问题
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232736
Kyuchull Kim, K. Saluja
{"title":"On fault deletion problem in concurrent fault simulation for synchronous sequential circuits","authors":"Kyuchull Kim, K. Saluja","doi":"10.1109/VTEST.1992.232736","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232736","url":null,"abstract":"A method for improving the performance of concurrent fault simulators for combinational and synchronous sequential circuits is proposed. The paper identifies two causes of inefficiencies and a simple and uniform method to eliminate them. A simulator, FASTS, based on the method proposed in the paper is implemented and it is shown that FASTS outperforms the existing concurrent simulation methods proposed in literature.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A functional BIST approach for FIR digital filters FIR数字滤波器的功能BIST方法
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232730
C. Counil, G. Cambon
{"title":"A functional BIST approach for FIR digital filters","authors":"C. Counil, G. Cambon","doi":"10.1109/VTEST.1992.232730","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232730","url":null,"abstract":"Presents a functional level built-in self-test of digital filters. This BIST technique is based on predetermined patterns which are not dependent on the filter implementation. Many examples show that stuck-at fault coverage is about 98%.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127477396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On-line testing of switched-capacitor filters 开关电容滤波器的在线测试
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232732
J. Huertas, D. Vázquez, A. Rueda
{"title":"On-line testing of switched-capacitor filters","authors":"J. Huertas, D. Vázquez, A. Rueda","doi":"10.1109/VTEST.1992.232732","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232732","url":null,"abstract":"Proposes a new solution to alleviate the area overhead when replication is used in switched-capacitor filters. This new approach, although based on the voter mechanism, only requires a programmable biquad and some control logic as extra components (instead of the full duplication of the system). To some extent, it can be considered a first intent to apply information redundancy for the concurrent test of analog circuits.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132505115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A concurrent checking scheme for single and multibit errors in logic circuits 逻辑电路中单比特和多比特错误的并发检测方案
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232742
B. Kolla, P. Lala, K. Yarlagadda
{"title":"A concurrent checking scheme for single and multibit errors in logic circuits","authors":"B. Kolla, P. Lala, K. Yarlagadda","doi":"10.1109/VTEST.1992.232742","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232742","url":null,"abstract":"A new scheme for detecting single and multibit (unidirectional and bidirectional) errors using residue codes has been proposed. This procedure has been applied to circuits with outputs up to 8 bits. It has been shown that about 99% of all multibit errors can be detected using this scheme.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131884180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Zero cost testing of check bits in RAMs with on-chip ECC 片上ECC对ram中校验位的零成本测试
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232768
P. Ramanathan, K. Saluja, Michael J. Franklin
{"title":"Zero cost testing of check bits in RAMs with on-chip ECC","authors":"P. Ramanathan, K. Saluja, Michael J. Franklin","doi":"10.1109/VTEST.1992.232768","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232768","url":null,"abstract":"The authors address the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding parity-check matrices such that all the check bits are tested while the information bits are being tested, without any increase in the length of the test sequence. The resulting parity-check matrix is such that there is no loss in error-correction capabilities and with minimal penalty in the worst-case delay of the error-correcting logic.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115970440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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