{"title":"Improving the theory of truth table verification of iterative logic arrays","authors":"M. Nicolaidis","doi":"10.1109/VTEST.1992.232776","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232776","url":null,"abstract":"The author shows that, if the number of the states of the reduced flow table of an iterative logic array (ILA) is not a power of 2, then, the truth table verification of the ILA requires to test it exhaustively. Thus, in this case the theory presented by F.J.O. Dias (1976) and allowing the truth table verification of ILAs by means of C-tests, is not valid. Then the author extends this theory to the case where the ILA cells have some inputs in common (such ILAs are for instance ALUs, and the rows of multiply and divide arrays).<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126844558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Checksum-based concurrent error detection in linear analog systems with second and higher order stages","authors":"A. Chatterjee","doi":"10.1109/VTEST.1992.232767","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232767","url":null,"abstract":"The problem of concurrent error detection in a class of linear analog systems containing second and higher order stages is discussed in this paper. Individual stages of such systems have transfer functions whose denominators contain the terms s/sup 2/,s/sup 3/,. . ., where s is the complex frequency of the transfer function H/sub i/(s) of the i'th stage. Such systems are widely used to realize a variety of analog and switched-capacitor filters and control systems. The author assumes that a fault can cause the value of a passive circuit component to deviate from its normal value, result in a short or an open line or change the operating characteristics of the operational amplifiers. A small amount of additional hardware is used to perform error detection, its size being virtually independent of the size of the circuit on which error detection is to be performed. Further, the sensitivity of the error detection scheme to changes in the component values can be easily adjusted.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Detection of multiple faults in CMOS circuits using a behavioral approach","authors":"Yinan N. Shen, F. Lombardi","doi":"10.1109/VTEST.1992.232747","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232747","url":null,"abstract":"Presents an approach for the detection of multiple stuck-open (SOP) and stuck-on (SON) faults in CMOS combinational logic circuits. It is proved that multiple SON and SOP faults do not mask each other. This is achieved using a behavioral analysis in which the maskable fault patterns are proved to be impossible. New testing approaches are proposed. Testing is implemented using a combination of two-pattern test sequences as well as universal test sets, as proposed in previous papers by different authors.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131924977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of low cost ROM based test generators","authors":"G. Edirisooriya, John P. Robinson","doi":"10.1109/VTEST.1992.232725","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232725","url":null,"abstract":"A data compression technique for ROM based built-in test generators of combinational circuits is described. Some of the test pattern bits are computed using the reduced data stored in the ROM combined with the address bits accessing the ROM. Some experimental results are presented for ISCAS benchmark circuits and random data.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133862779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Algorithms for the design verification of bipolar array chips","authors":"D. Zein, Oliver P. Engel, G. Ditlow","doi":"10.1109/VTEST.1992.232774","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232774","url":null,"abstract":"A new methodology is used for the design verification of bipolar array chips. Here the authors apply analog methods to verify the logic function of the chip's basic circuits or macromodels and the noise margins. They also check for reliability by computing the current density at each device contact stud. The logic paths are implicitly verified. Several algorithms are used as building blocks in an implementation program. This includes a recursive scheduling algorithm, a Gray algorithm and an algorithm to treat differential pairs. A nonlinear Gauss-Seidel method for decoupling and solving a nonlinear set of algebraic equations is described.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132696490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On test generation for combinational circuits consisting of AND and EXOR gates","authors":"S. Toida, N. Rao","doi":"10.1109/VTEST.1992.232734","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232734","url":null,"abstract":"Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124085897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multiple redundancy removal during test generation and synthesis","authors":"David M. Wu, R. M. Swanson","doi":"10.1109/VTEST.1992.232765","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232765","url":null,"abstract":"Techniques of multiple redundancy removal (MRFE) during test generation are described in this paper. A redundant fault, once identified, is propagated forward and backward through the sensitized paths to identify other redundant faults in the circuit under test. The technique is also applied to the class of 'dropped faults' and 'untested faults'. This technique can also be applied to logic minimization during synthesis.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130300681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Developments in delay testing","authors":"J. Savir","doi":"10.1109/VTEST.1992.232760","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232760","url":null,"abstract":"The author's objective is to introduce the reader to the fast emerging field of AC test for digital logic circuits. He includes a brief discussion of the important concepts, algorithms and circuits that are used in conjunction with AC test. A comprehensive bibliography is provided.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129663815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-testing and self-checking combinational circuits with weakly independent outputs","authors":"E. Sogomonyan, M. Gössel","doi":"10.1109/VTEST.1992.232769","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232769","url":null,"abstract":"The authors propose a structure dependent method for the systematic design of self-checking error detection circuits which is well adapted to the technical fault model considered. For online detection, the hardware is in normal operation mode, and for testing in test mode. In the test mode, these error detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129784370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A methodology for the insertion of a hierarchical and boundary-scan compatible self test","authors":"O. Haberl, T. Kropf","doi":"10.1109/VTEST.1992.232721","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232721","url":null,"abstract":"A methodology is presented, which automatically embeds a self test architecture into hierarchically designed circuits. For each module of the design hierarchy the automatic method for the insertion of self test registers as well as the synthesis of a test control unit is presented. These self testable modules are then combined for arbitrary hierarchy levels using test management units. The concept is embedded within the boundary-scan architecture and the implementation has been integrated into a commercial design framework.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122460460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}