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Digest of Papers. 1992 IEEE VLSI Test Symposium最新文献

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Data driven neural-based measurement discrimination for IC parametric faults diagnosis 基于数据驱动神经测量判别的集成电路参数故障诊断
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232748
A. Wu, J. Meador
{"title":"Data driven neural-based measurement discrimination for IC parametric faults diagnosis","authors":"A. Wu, J. Meador","doi":"10.1109/VTEST.1992.232748","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232748","url":null,"abstract":"Describes experimental results obtained with the use of data driven neural-based system for statistical IC fault diagnosis. Measurement discrimination is established through a reduction method involving data pre-processing in a fashion consistent with a specific definition of parametric faults. The effects of this preprocessing are examined in the context of a realistic IC parametric fault diagnostic problem.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129942295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Built-in current self-testing scheme (BICST) for CMOS logic circuits 内置电流自测方案(BICST)的CMOS逻辑电路
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232770
C. Tong
{"title":"Built-in current self-testing scheme (BICST) for CMOS logic circuits","authors":"C. Tong","doi":"10.1109/VTEST.1992.232770","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232770","url":null,"abstract":"A novel scheme for built-in self-testing used in current testing environment (named BICST) is presented in this paper. Test vectors are generated on chip in BICST to detect the stuck-on and bridging faults as well as stuck-at faults in a CMOS circuit. The test set generated by pseudo-exhaustive testing method can detect stuck-on and bridging faults that cause abnormal large current flow in the circuit, which will be caught by the built-in current sensors. Partitioning is done for pseudo-exhaustive testing and to obtain high resolution in current measuring. The overall structure of the BICST system is also presented.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132839852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test pattern generation system for delay faults using a high speed simulation processor 'SP' 基于高速模拟处理器“SP”的延迟故障模式生成测试系统
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232717
Yukiko Izuta, F. Hirose
{"title":"Test pattern generation system for delay faults using a high speed simulation processor 'SP'","authors":"Yukiko Izuta, F. Hirose","doi":"10.1109/VTEST.1992.232717","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232717","url":null,"abstract":"The degree of needs for high quality test pattern sets for delay faults becomes more serious as VLSI chips have more complex structures and higher performance. In spite of its importance, it is more difficult to find complete test pattern sets for delay faults than for stuck-at faults. It thus takes much time to generate high quality test pattern sets. To acquire high quality test pattern sets for delay faults as fast as possible, the authors take an approach that executes a test pattern generation process for delay faults on the very high speed logic simulation processor 'SP'. As a result, to apply ISCAS'89 benchmark circuits, the authors achieved a fault coverage rate of 85% in two minutes testing for a circuit which has about 1000 gates. They confirmed that this system is effective as a pre-processing method to exclude many faults at very highspeed.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130694665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Behavior of faulty single BJT BiCMOS logic gates 故障单BJT BiCMOS逻辑门的行为
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232772
S. Menon, Y. Malaiya, A. Jayasumana
{"title":"Behavior of faulty single BJT BiCMOS logic gates","authors":"S. Menon, Y. Malaiya, A. Jayasumana","doi":"10.1109/VTEST.1992.232772","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232772","url":null,"abstract":"The logic behavior of single BJT BiCMOS devices under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behaviour of bipolar (TTL) and CMOS logic families is compared with BiCMOS. Effects of bridging faults in BiCMOS devices has been examined for both hard short as well as bridging with a significant resistance.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114803901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Generalization of independent faults for transition faults 过渡故障的独立故障推广
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232716
I. Pomeranz, S. Reddy
{"title":"Generalization of independent faults for transition faults","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/VTEST.1992.232716","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232716","url":null,"abstract":"Independent faults were shown to he effective in computing small test sets for stuck-at faults. An efficient procedure for computing a maximal set of independent stuck-at faults is proposed. The notion of independent faults is then extended to other fault models, specifically, transition faults, that require two-pattern tests. Experimental results are presented to show that the computation of independent faults can be practically performed.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124240500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On test generation for path delay faults in ASICs asic中路径延迟故障的测试生成
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232718
P. Varma
{"title":"On test generation for path delay faults in ASICs","authors":"P. Varma","doi":"10.1109/VTEST.1992.232718","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232718","url":null,"abstract":"Discusses automatic test pattern generation (ATPG) for path delay faults in application specific integrated circuits (ASICs). An ATPG that uses a modified FAN algorithm to generate tests for critical paths derived using static timing analysis is described. The test generation procedure is optimised through the use of path constrainment and the concept of mandatory assignments.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124851926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Built-in self-test design for large embedded PLAs 内置自检设计，用于大型嵌入式PLAs
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232727
Alicja Pierzynska, S. Pilarski
{"title":"Built-in self-test design for large embedded PLAs","authors":"Alicja Pierzynska, S. Pilarski","doi":"10.1109/VTEST.1992.232727","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232727","url":null,"abstract":"Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130176858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Redundancy removal and simplification of combinational circuits 组合电路的冗余去除和简化
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232764
P. R. Menon, Hitesh Ahuja
{"title":"Redundancy removal and simplification of combinational circuits","authors":"P. R. Menon, Hitesh Ahuja","doi":"10.1109/VTEST.1992.232764","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232764","url":null,"abstract":"Redundancy in combinational circuits is usually identified when faults are found to be undetectable during test generation. Redundancy removal based on test generation is not efficient, because removal of the redundancy causing a fault to be undetectable will usually affect the detectability of other faults, making it necessary to repeat test generation. The authors present a method of identifying and removing redundancy in combinational circuits by analyzing regions between fanout stems and reconvergence gates, and experimental results for the ISCAS85 benchmark circuits.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129785629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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