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Digest of Papers. 1992 IEEE VLSI Test Symposium最新文献

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On the effectiveness of simultaneous self-test techniques 论同步自测技术的有效性
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232726
Peter A. Johnson, F. Ferguson
{"title":"On the effectiveness of simultaneous self-test techniques","authors":"Peter A. Johnson, F. Ferguson","doi":"10.1109/VTEST.1992.232726","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232726","url":null,"abstract":"Describes a built-in self-test (BIST) technique for general sequential circuits in which storage elements in a circuit are replaced with self-test elements. These elements are connected as a feedback shift register, and used to both generate test patterns and compress test responses. Benchmarks were run on a number of standard sequential benchmark circuits to determine single stuck-at fault coverage. The results of these tests indicate that the self-test techniques presented obtain fault coverage similar to that of random test techniques.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122178639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation 基于上一代成成率分析的新一代eprom冗余优化设计
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232746
K. Imamiya, J. Miyamoto, N. Ohtuska, N. Tomita, Y. Iyama
{"title":"Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation","authors":"K. Imamiya, J. Miyamoto, N. Ohtuska, N. Tomita, Y. Iyama","doi":"10.1109/VTEST.1992.232746","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232746","url":null,"abstract":"Failure modes of 4 Mbit EPROMs have been analyzed, and the model to formulate them is proposed. The redundancy scheme of a 16 Mbit EPROM was optimized by the model in consideration of area penalty. In applying the 4 Mbit data to 16 Mbit EPROM, fabrication line improvement was taken into account. The actual data of 16 Mbit EPROM failure analysis indicate the effectiveness of the prediction. The 16 Mbit EPROM has 2 rows*8 blocks redundancy, and the redundancy gives the highest yield in the time when the mass production begins.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125148449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accelerated path delay fault simulation 加速路径延迟故障仿真
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232715
Yuejian Wu, A. Ivanov
{"title":"Accelerated path delay fault simulation","authors":"Yuejian Wu, A. Ivanov","doi":"10.1109/VTEST.1992.232715","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232715","url":null,"abstract":"Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure for path delay fault simulation whereby each node of the simulated circuit is evaluated only once per simulation pass in the backtrace process. Experiments with the ISCAS'85 benchmark circuits show that the procedure accelerates path delay fault simulation significantly. The proposed procedure can be implemented for parallel pattern path delay fault simulation. The concepts of SES and SESR can also improve both CPU time and memory efficiency of path delay fault simulation if only a subset of all the paths is considered.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121946096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Simulation of physical faults in VLSI circuits VLSI电路中物理故障的仿真
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232750
I. Hajj, Terry Lee
{"title":"Simulation of physical faults in VLSI circuits","authors":"I. Hajj, Terry Lee","doi":"10.1109/VTEST.1992.232750","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232750","url":null,"abstract":"Describes an approach for performing transistor-level logical fault simulation of VLSI MOS circuits. The method is based on a recently introduced algebraic approach to switch-level simulation. The faults considered are grouped into four sets: node stuck-at, transistor stuck-open, transistor stuck-on, and bridging faults. The authors consider concurrent fault simulation implementation, and compare, using typical examples, the computational and storage requirements of including all faults in the fault list in one simulation run versus using multiple runs with different fault groupings. Both output voltage and supply current monitoring are used for fault detection.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132279074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A design for testability scheme to reduce test application time in full scan 一种可测试性方案的设计，以减少全扫描时的测试应用时间
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232724
D. Pradhan, Jayashree Saxena
{"title":"A design for testability scheme to reduce test application time in full scan","authors":"D. Pradhan, Jayashree Saxena","doi":"10.1109/VTEST.1992.232724","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232724","url":null,"abstract":"Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134379667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Empirical bounds on fault coverage loss due to LFSR aliasing LFSR混叠导致故障覆盖损失的经验界
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232739
W. Debany, M. Gorniak, D. Daskiewich, A. Macera, K. Kwiat, H. Dussault
{"title":"Empirical bounds on fault coverage loss due to LFSR aliasing","authors":"W. Debany, M. Gorniak, D. Daskiewich, A. Macera, K. Kwiat, H. Dussault","doi":"10.1109/VTEST.1992.232739","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232739","url":null,"abstract":"Linear-feedback shift registers (LFSRs) are often used to compact test responses. Prior analyses, based on statistically-independent error models, have predicted that aliasing probability 'converges' to 2/sup -k/ for LFSR polynomials of degree k, and that primitive polynomials perform better than nonprimitive polynomials. This paper presents the first statistical results based on full fault simulation that confirm these predictions. However, the average aliasing probability is not by itself a useful measure of the loss of fault detection information; the authors introduce an upper confidence limit (UCL) for the loss of fault coverage. The 'ideal' UCL is shown to match closely the empirically-derived UCL.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127644982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Effective concurrent test for a parallel-input multiplier using modulo 3 使用模3的并联输入乘法器的有效并发测试
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232766
W. Debany, A. Macera, D. Daskiewich, M. Gorniak, K. Kwiat, H. Dussault
{"title":"Effective concurrent test for a parallel-input multiplier using modulo 3","authors":"W. Debany, A. Macera, D. Daskiewich, M. Gorniak, K. Kwiat, H. Dussault","doi":"10.1109/VTEST.1992.232766","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232766","url":null,"abstract":"Experiments were performed to determine the effectiveness of modulo 3 checking for a class of two's complement, parallel-input multipliers. A full gate-level simulation of stuck-at faults was performed. The probability of aliasing for a 12*12-bit multiplier was found to be only 5.196%. The assumption that bit errors are statistically-independent yields a much greater probability of aliasing.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116853141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An investigation of circuit partitioning for parallel test generation 并行测试生成电路划分的研究
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232735
S. Bollinger, S. Midkiff
{"title":"An investigation of circuit partitioning for parallel test generation","authors":"S. Bollinger, S. Midkiff","doi":"10.1109/VTEST.1992.232735","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232735","url":null,"abstract":"Explores the feasibility of using circuit partitioning approach to reduce the run-time complexity of test generation via parallel processing. Characterization of the major phases of test generation is used to show how the inherent parallelism existing in test generation can be exploited during forward implication and backward justification. Upper bounds on the concurrency available in specific are empirically determined by simulating the behavior of a 'perfect' conflict-free test generation algorithm that operates without backtracking. Results presented for a number of benchmark circuits indicate that the average available parallelism is fairly low, limiting the potential speedup of a circuit partitioning approach to test generation.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116207660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Delay fault testing of iterative arithmetic arrays 迭代算术数组的延迟故障测试
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232719
R. Roy, N. Nagi, A. Chatterjee, M. d'Abreu
{"title":"Delay fault testing of iterative arithmetic arrays","authors":"R. Roy, N. Nagi, A. Chatterjee, M. d'Abreu","doi":"10.1109/VTEST.1992.232719","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232719","url":null,"abstract":"Delay fault testing of iterative arithmetic arrays (IAAs) is important because IAAs contain long critical paths and often determine the clock speed. A new approach, based on a weighted graph model has been developed that exploits the regularity of IAAs to select paths to be tested, and generates delay fault tests for those paths. The number of longest paths in an IAA grows exponentially with the dimension of the IAA, but the technique tests only a selected subset of longest paths, whose size is linear in the dimension of the IAA. A Monte-Carlo simulation was performed to ascertain the detection of delay faults in paths that were not explicitly tested. Promising results were obtained.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"64 5-6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120903921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HLSIM-a new hierarchical logic simulator in APL hlsim -一种新的APL层次逻辑模拟器
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232775
D. Zein, Oliver P. Engel, G. Ditlow
{"title":"HLSIM-a new hierarchical logic simulator in APL","authors":"D. Zein, Oliver P. Engel, G. Ditlow","doi":"10.1109/VTEST.1992.232775","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232775","url":null,"abstract":"HLSIM is an APL hierarchical logic simulator that can deal with nested models. The program has all the facilities to handle large VLSI circuits with complicated sequential logic, including full chip simulation. The authors discuss two major programs: an analog to digital netlist converter and a new digital simulator implemented in APL, a natural environment for logic simulators, especially when its powerful APL nested array facilities are used. The netlist converter takes a hierarchical analog netlist and supplementary files for the leaf models, and creates a digital model of the VLSI circuit. A discussion of the simulator includes its data structure, two algorithms for the static (zero) and the dynamic (unit or variable) delay modes of simulation. The authors also discuss how to handle unique features of the bipolar circuits including emitter, collector dots and differential pairs. Three types of gates can be used: primitive, truth tables, and behavioral models implemented as arbitrary user functions. The last feature enabled them to model and simulate complicated bipolar chips and decoders.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123189258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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