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Digest of Papers. 1992 IEEE VLSI Test Symposium最新文献

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Analysis of the die test optimization algorithm for negative binomial yield statistics 负二项良率统计的模具试模优化算法分析
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232745
C. M. Krishna, A. Singh
{"title":"Analysis of the die test optimization algorithm for negative binomial yield statistics","authors":"C. M. Krishna, A. Singh","doi":"10.1109/VTEST.1992.232745","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232745","url":null,"abstract":"Introduces a new adaptive testing algorithm that uses spatial defect clustering information and available test from neighbouring dies to optimize test lengths during wafer-probe testing. When applied to the defect distribution data for 12 sample wafers collected by Saji and Armstrong, the new approach showed potential for providing improvement in overall product quality. In this paper, the authors conduct a more general study to evaluate the proposed new test optimization algorithm based on the widely accepted negative binomial model for defect distributions on a wafer. The objective is to obtain a more accurate measure of the magnitude of the defect-level improvements that can be expected under various yield and defect-clustering conditions.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123767192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The roles of controllability and observability in design for test 可控性和可观察性在测试设计中的作用
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232754
K. Butler, R. Kapur, M. R. Mercer, D. Ross
{"title":"The roles of controllability and observability in design for test","authors":"K. Butler, R. Kapur, M. R. Mercer, D. Ross","doi":"10.1109/VTEST.1992.232754","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232754","url":null,"abstract":"The nature of many problems related to testability requires detailed information about their underlying test parameters. These parameters are commonly referred to as controllability and observability. This research concerns exact measures of detectability, controllability, and observability to measure the relative importance of the latter two on the likelihood of the former. New functional methods for fault analysis are utilized which allow computations not previously possible; the empirical results presented here are an example of such an application.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122493342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A mixed signal tester solution for: standards traceable AC calibration of analog modules 一个混合信号测试仪解决方案:标准可追溯的交流校准模拟模块
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232729
M. F. Abate
{"title":"A mixed signal tester solution for: standards traceable AC calibration of analog modules","authors":"M. F. Abate","doi":"10.1109/VTEST.1992.232729","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232729","url":null,"abstract":"Presents a mixed signal test system architecture focused at reducing the overall cost of test. Illustrated are the tester architecture, accuracy and traceability achievements, as well as the benefits realized in the reduction of factors contributing to the overall cost of test.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128048846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent advances in logic synthesis with testability 具有可测试性的逻辑综合的最新进展
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232761
J. Rajski, J. Vasudevamurthy, A. El-Maleh
{"title":"Recent advances in logic synthesis with testability","authors":"J. Rajski, J. Vasudevamurthy, A. El-Maleh","doi":"10.1109/VTEST.1992.232761","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232761","url":null,"abstract":"The primary consideration in the entire logic synthesis process is the quality of the resulting circuit measured by its speed, chip area, and recently also testability. The crucial phase in automatic logic synthesis, where all these parameters are determined, is the process of decomposition and factorization which generates multilevel Boolean equations for the synthesized circuit. There are a number of various aspects of testability. These aspects depend on the fault models and testing strategies used. One of the basic objectives is to synthesize circuits that are completely testable for a given class of faults.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132159614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A simulation-based approach to test pattern generation for synchronous sequential circuits 基于仿真的同步顺序电路测试模式生成方法
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232763
P. Camurati, Fulvio Corno, Fulvio Prinetto, M. Reorda
{"title":"A simulation-based approach to test pattern generation for synchronous sequential circuits","authors":"P. Camurati, Fulvio Corno, Fulvio Prinetto, M. Reorda","doi":"10.1109/VTEST.1992.232763","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232763","url":null,"abstract":"Particular design environments, e.g., those based on partial scan, may prevent design for testability techniques from reducing testing to a combinational problem: ATPG for sequential devices thus remains a challenge. Random and deterministic structure-oriented techniques are state-of-the-art, but there is a growing interest in methods that resort to the automaton of the circuit. The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode. SETA generates test patterns while trying to disprove the equivalence of two automata. SETA is simulation-based: within the theoretical framework of the product machine, state-of-the-art simulation techniques are used to yield satisfactory experimental results on the ISCAS89 benchmark set.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114765729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults 一种针对卡断故障的CMOS电路全自检设计新技术
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232741
M. S. Cheema, P. Lala
{"title":"A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults","authors":"M. S. Cheema, P. Lala","doi":"10.1109/VTEST.1992.232741","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232741","url":null,"abstract":"Presents a new technique for designing single stage fully complementary metal oxide semiconductor (FCMOS) and CMOS domino logic circuits so that they are totally self checking for all single s-off and s-on faults. It involves the encoding of the output of the circuit in an error detecting code. CMOS circuits designed using the technique have two outputs. Two of the combinations (01,10) are considered to be valid code-words. The circuit is augmented such that any stuck-off (stuck-on) fault in the modified circuit produces a non-valid output 11(00), thus ensuring automatic fault detection.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"24 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent advances in sequential test generation 顺序测试生成的最新进展
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232759
K. Cheng
{"title":"Recent advances in sequential test generation","authors":"K. Cheng","doi":"10.1109/VTEST.1992.232759","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232759","url":null,"abstract":"The author gives a short review of recent developments in automatic test generation for sequential circuits. Approaches are classified according to the level of abstraction at which the circuit is described. The basic concepts, advantages, disadvantages, and application domains of representative methods of each class are discussed.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123389299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On-chip current sensing circuit for CMOS VLSI CMOS VLSI片上电流传感电路
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232771
Tung-Li Shen, J. Daly, Jien-Chung Lo
{"title":"On-chip current sensing circuit for CMOS VLSI","authors":"Tung-Li Shen, J. Daly, Jien-Chung Lo","doi":"10.1109/VTEST.1992.232771","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232771","url":null,"abstract":"CMOS is a popular technology today for very large scale integrated (VLSI) circuits. But, conventional functional testing cannot guarantee the detection of some defects. Built-in current testing has been suggested to enhance the defect coverage. In this paper, the authors present a high-speed built-in current sensing (BICS) circuit design. An experimental CMOS VLSI chip containing BICS is described. The power bus current of an 8*8 parallel multiplier is monitored. This BICS detects all implanted short circuit defects and some open circuit defects at a clock speed of 30 MHz (limited by the test set up). SPICE3 simulations indicate a defect detection time of 2 ns.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116232848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Robust switch-level test generation 稳健的开关级测试生成
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232733
B. Mathew, D. Saab
{"title":"Robust switch-level test generation","authors":"B. Mathew, D. Saab","doi":"10.1109/VTEST.1992.232733","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232733","url":null,"abstract":"Metal oxide semiconductor (MOS) technology is highly popular currently due to the many advantages that it provides. It has been shown that conventional methods of testing are not applicable to MOS circuits. A switch-level model is used to generate a sequence of test vectors for a variety of MOS circuits, including those containing pass transistor logic.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116545263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Recent advances in BIST BIST的最新进展
Digest of Papers. 1992 IEEE VLSI Test Symposium Pub Date : 1992-04-07 DOI: 10.1109/VTEST.1992.232758
S. Gupta
{"title":"Recent advances in BIST","authors":"S. Gupta","doi":"10.1109/VTEST.1992.232758","DOIUrl":"https://doi.org/10.1109/VTEST.1992.232758","url":null,"abstract":"The author briefly reviews various recent results in data compression for BIST. His primary focus is on MISR compression, considering the practical design issues that interest a designer. Issues related to the choice of error model, feedback polynomial, and suitable test lengths are discussed.<<ETX>>","PeriodicalId":434977,"journal":{"name":"Digest of Papers. 1992 IEEE VLSI Test Symposium","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122759661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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