Test pattern generation system for delay faults using a high speed simulation processor 'SP'

Abstract

The degree of needs for high quality test pattern sets for delay faults becomes more serious as VLSI chips have more complex structures and higher performance. In spite of its importance, it is more difficult to find complete test pattern sets for delay faults than for stuck-at faults. It thus takes much time to generate high quality test pattern sets. To acquire high quality test pattern sets for delay faults as fast as possible, the authors take an approach that executes a test pattern generation process for delay faults on the very high speed logic simulation processor 'SP'. As a result, to apply ISCAS'89 benchmark circuits, the authors achieved a fault coverage rate of 85% in two minutes testing for a circuit which has about 1000 gates. They confirmed that this system is effective as a pre-processing method to exclude many faults at very highspeed.<>