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2005 6th International Conference on ASIC最新文献

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A CMOS correlator for UWB front-end circuit 一种用于超宽带前端电路的CMOS相关器
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611364
Chunjiang Tu, Boan Liu, Hongyi Chen
{"title":"A CMOS correlator for UWB front-end circuit","authors":"Chunjiang Tu, Boan Liu, Hongyi Chen","doi":"10.1109/ICASIC.2005.1611364","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611364","url":null,"abstract":"A CMOS analog correlator designed using SMIC/spl reg/ 0.18/spl mu/m CMOS mixed and RF technology is proposed in this paper. The correlator is mainly composed of a Gilbert cell, common mode feedback (CMFB) circuit, capacitor load and buffer. The correlator can be used in the ultra wideband (UWB) receivers.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131901687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection 一种用于高速片上异步互连的低摆幅差分接口电路
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611256
Huazhong Yang, F. Qiao, Gang Huang, Hui Wang
{"title":"A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection","authors":"Huazhong Yang, F. Qiao, Gang Huang, Hui Wang","doi":"10.1109/ICASIC.2005.1611256","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611256","url":null,"abstract":"A novel low-swing interface circuit for asynchronous interconnection is proposed in this paper. It takes a level-triggered differential latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the method of driver-array (Fei Qiao et al., 2003) .The proposed circuit consumes less power than previously reported designs and can work up to 500 MHz, which is simulated and fabricated with SMIC 0.18-mum 1.8-V digital CMOS technology","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133064427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a high-speed low-power CAM 高速低功耗凸轮的设计
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611281
Canghai Gu, Hefei Zhu, Xiaofang Zhou, Hao Min, Dian Zhou
{"title":"Design of a high-speed low-power CAM","authors":"Canghai Gu, Hefei Zhu, Xiaofang Zhou, Hao Min, Dian Zhou","doi":"10.1109/ICASIC.2005.1611281","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611281","url":null,"abstract":"A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133464258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and implementation of DFT strategy in ASIC design of resilient packet ring 弹性分组环ASIC设计中DFT策略的设计与实现
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611415
Fan Zhang, Jishi Li, Hong Chen, Depeng Jin, Lieguang Zeng
{"title":"Design and implementation of DFT strategy in ASIC design of resilient packet ring","authors":"Fan Zhang, Jishi Li, Hong Chen, Depeng Jin, Lieguang Zeng","doi":"10.1109/ICASIC.2005.1611415","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611415","url":null,"abstract":"According to the practical test requirements of resilient packet ring (RPR) application specific integrated circuit (ASIC), design for testability (DFT) strategy that applies three different DFT methods compositively is proposed in this paper. Principles and key methods used in the strategy are introduced, including scan chain, boundary scan test (BST), memory built-in-self-test (MBIST). Implementation process and results of the DFT strategy are analyzed in detail. DFT circuits implemented in RPR ASIC have reduced the difficulty of test and improved fault coverage a lot. Adopting DFT techniques logically and compositively is very important","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128993860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new algorithm of digital matched filter with a segment processing method 基于分段处理的数字匹配滤波新算法
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611310
Xuan Guan, Jing Chen
{"title":"A new algorithm of digital matched filter with a segment processing method","authors":"Xuan Guan, Jing Chen","doi":"10.1109/ICASIC.2005.1611310","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611310","url":null,"abstract":"In this paper, a novel segment processing matched filter algorithm is proposed by optimizing the differential digital matched filter (DDMF) structure. According to the new architecture, the computation complexity of DMF can be reduced to approximately 30% of that of the DDMF for fixed coefficient PN sequence. To further reduce the area and power consumption, several strategies have been employed. This design was successfully tested as a component for an acquisition circuit to be used in Global Positioning System (GPS) receiver (Braasch and van Dierendonck, 1999), and was able to operate at up to 100MHz","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131577046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new FPGA packing algorithm based on the modeling method for logic block 一种基于逻辑块建模方法的FPGA封装算法
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611445
Gang Ni, J. Tong, Jinmei Lai
{"title":"A new FPGA packing algorithm based on the modeling method for logic block","authors":"Gang Ni, J. Tong, Jinmei Lai","doi":"10.1109/ICASIC.2005.1611445","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611445","url":null,"abstract":"Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127767198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fast and efficiently binding of functional units for low power design 快速有效地绑定功能单元，实现低功耗设计
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611258
Zhipeng Liu, Jinian Bian, Jianfeng Huang, Yunfeng Wang
{"title":"Fast and efficiently binding of functional units for low power design","authors":"Zhipeng Liu, Jinian Bian, Jianfeng Huang, Yunfeng Wang","doi":"10.1109/ICASIC.2005.1611258","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611258","url":null,"abstract":"In this paper, we present a parallel optimizing algorithm for fast and efficiently binding the functional units in high-level synthesis, so as to minimize the power dissipations and run-times. It has been founded on the observation that different binding results will significantly affect the total number of switching activities (SW) of functional units, and further will affect the power dissipation. Also, the run-time for binding is considerable. Unlike many other previously proposed methods, our approach considers not only the minimizing of switching activities, but also the reducing of run-times for binding. Experimental results on benchmarks indicate that our designs are 11%-32% more power-efficient than the results produced by random binding. Furthermore, in terms of run-times as well as the switching activities, our approach makes an improvement on the circuit performance by 8.4% over the already existing power-optimized binding technique based on multistage graph methodology","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127921307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 14-/spl mu/A 3-ppm//spl deg/C CMOS bandgap voltage reference 一个14-/spl μ /A 3-ppm//spl度/C CMOS带隙基准电压
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611366
Chunhua Yao, Boan Liu, Yuwen Xia
{"title":"A 14-/spl mu/A 3-ppm//spl deg/C CMOS bandgap voltage reference","authors":"Chunhua Yao, Boan Liu, Yuwen Xia","doi":"10.1109/ICASIC.2005.1611366","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611366","url":null,"abstract":"The work presented in this paper improves on a high order curvature-compensated CMOS band-gap reference circuit design. A cascoded current mirror is utilized in order to increase the bandgap voltage's power supply rejection ratio (PSRR) and decrease the mismatch current. A source follower is inserted in series with the capacitor to guarantee the system stable. Simulated in the standard 0.18mum CMOS technology, the proposed voltage reference can operate down to 1.5V supply and consumes supply current of 14muA. A temperature coefficient of 3-ppm/degC is achieved through the temperature-dependent resistor ratio","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129138140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation of low-voltage true-single-phase-clocking (TSPC) logic using bulk dynamic threshold MOS technique 采用批量动态阈值MOS技术实现低压真单相时钟逻辑
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611287
Keng C. Wu, S. Jia, Zhongjian Chen, Xuewen Gan
{"title":"Implementation of low-voltage true-single-phase-clocking (TSPC) logic using bulk dynamic threshold MOS technique","authors":"Keng C. Wu, S. Jia, Zhongjian Chen, Xuewen Gan","doi":"10.1109/ICASIC.2005.1611287","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611287","url":null,"abstract":"Dynamic threshold MOS circuits can adjust devices' threshold according to the states of the circuits and thus offer higher speed and better saving of energy at low voltage. In this paper a new fast bulk true single phase clocking (TSPC) dynamic threshold MOS scheme for both NMOS and PMOS is introduced. In this scheme the common substrate of the NMOS logic or PMOS logic is dynamically controlled: the potential changes only when these transistors need to work and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate, to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulation","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128415555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimizing SoC platform architecture for multimedia applications 优化SoC平台架构的多媒体应用
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611247
Tang Lei, Yang Yanhui, Wei Shao-jun
{"title":"Optimizing SoC platform architecture for multimedia applications","authors":"Tang Lei, Yang Yanhui, Wei Shao-jun","doi":"10.1109/ICASIC.2005.1611247","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611247","url":null,"abstract":"As system-on-chip (SoC) will soon become the whole world electronic production mainstream in the near future, Datang Microelectronics Technology Co., LTD., Beijing, China, is now focusing on SoC platform based hardware designs and software applications as a pioneer. In this paper, a typical research case is described on how to optimizing a SoC architecture for multimedia applications. ConvergenSC, one of CoWare Corporation's electronic system level design tool, helped us greatly on structuring a series virtual SoC architectures, and then quickly getting all kinds of performance analysis results according to the corresponding virtual SoC architecture. With its aids, we easily got our best design result","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116904070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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