Design of a high-speed low-power CAM

Abstract

A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB