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2005 6th International Conference on ASIC最新文献

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A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers 用于WPAN接收机的CMOS连续时间Gm-C滤波器和可编程增益放大器
2005 6th International Conference on ASIC Pub Date : 2008-06-15 DOI: 10.1109/SNW.2008.5418398
Yeon-kug Moon, H. Seo, Kwang-Ho Won, Yong-Kuk Park, Myunghyun Yoon, Jun-Jae Yoo, Seong-Dong Kim
{"title":"A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers","authors":"Yeon-kug Moon, H. Seo, Kwang-Ho Won, Yong-Kuk Park, Myunghyun Yoon, Jun-Jae Yoo, Seong-Dong Kim","doi":"10.1109/SNW.2008.5418398","DOIUrl":"https://doi.org/10.1109/SNW.2008.5418398","url":null,"abstract":"This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve low current consumption. High linearity and constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18mum 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of 0.19mm2","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126783998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power reduction in high-speed inter-chip data communications 高速芯片间数据通信的功耗降低
2005 6th International Conference on ASIC Pub Date : 2005-12-01 DOI: 10.1109/ICASIC.2005.1611234
T. Kuroda
{"title":"Power reduction in high-speed inter-chip data communications","authors":"T. Kuroda","doi":"10.1109/ICASIC.2005.1611234","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611234","url":null,"abstract":"This paper describes power reduction techniques in high-speed inter-chip data communication with inductive coupled wireless interface for 3D-stacked SiP. NRZ signaling where signal is not transmitted when data holds reduces power dissipation in proportion to switching activity. A low-power single-end transmitter is presented for 55% transmitter's power reduction. Depending on communication distance, transmit power is controlled for both power and crosstalk reduction. 195Gb/s, 1.2W high-speed and low-power interface with these techniques has been demonstrated in 0.25mum CMOS","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128920597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transition traversal coverage estimation for symbolic model checking 用于符号模型检查的转换遍历覆盖估计
2005 6th International Conference on ASIC Pub Date : 2005-12-01 DOI: 10.1109/ICASIC.2005.1611460
X. Xu, S. Kimura, K. Horikawa, T. Tsuchiya
{"title":"Transition traversal coverage estimation for symbolic model checking","authors":"X. Xu, S. Kimura, K. Horikawa, T. Tsuchiya","doi":"10.1109/ICASIC.2005.1611460","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611460","url":null,"abstract":"Model checking can exhaustively verify a set of specified properties on a given implementation. However, it is very hard to determine whether sufficient properties have been specified or not. In this paper, we propose a transition traversal coverage method for a subset of CTL to evaluate the completeness of properties. With this method, we can detect the transitions which are not verified by any property. It is more comprehensive and accurate than state-based coverage metric. We avoid generating the perturbed implementation by directly traversing transitions based on the semantics of CTL formulas. Experimental results show that the proposed method can discover subtle coverage holes with low computation cost.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126159205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A VLSI architecture for motion compensation interpolation in H.264/AVC H.264/AVC中运动补偿插值的VLSI架构
2005 6th International Conference on ASIC Pub Date : 2005-12-01 DOI: 10.1109/ICASIC.2005.1611300
Yang Song, Zhenyu Liu, S. Goto, T. Ikenaga
{"title":"A VLSI architecture for motion compensation interpolation in H.264/AVC","authors":"Yang Song, Zhenyu Liu, S. Goto, T. Ikenaga","doi":"10.1109/ICASIC.2005.1611300","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611300","url":null,"abstract":"A VLSI architecture for motion estimation/compensation interpolation in H.264/AVC is presented in this paper. Compared with previous work, this architecture has following characteristics: First, it supports all block modes and fractional samples adopted in H.264/AVC standard. Second, no extra initiation and finalization time is required, which enhances the system performance. Third, a pipelined finite impulse filter (FIR) is used to replace the traditional adder tree, which increases the system clock frequency. Because this design applies full pipelined architecture, it can generate one half sample in every cycle and eight quarter samples in every nine cycles with little pipeline latency. In fact, this architecture with minor revision could be adopted in MPEG-4 and other video coding standards. The design is implemented with TSMC 0.18/spl mu/m CMOS technology. The core area is 0.577/spl times/0.661mm/sup 2/ and frequency is 274MHz in typical condition (1.8V, 25/spl deg/C).","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Low power SRAM design using charge sharing technique 采用电荷共享技术的低功耗SRAM设计
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611260
Gu Ming, Yang Jun, Xue Jun
{"title":"Low power SRAM design using charge sharing technique","authors":"Gu Ming, Yang Jun, Xue Jun","doi":"10.1109/ICASIC.2005.1611260","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611260","url":null,"abstract":"This paper describes a low-power write scheme by adopting charge sharing technique. By reducing the bit lines voltage swing, the bit lines dynamic power is reduced. The memory cell's static noise margin (SNM) is discussed to prove it is a feasible scheme. Simulation results show compare to conventional SRAM, in write cycle this SRAM saves more than 20% dynamic power","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115124857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A novel method for the construction of self-dual circuits 一种构造自对偶电路的新方法
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611421
Wang Wei, Jianhui Jiang
{"title":"A novel method for the construction of self-dual circuits","authors":"Wang Wei, Jianhui Jiang","doi":"10.1109/ICASIC.2005.1611421","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611421","url":null,"abstract":"This paper presents a more area-effective method to construct self-dual circuits. The experimental results based on ISCAS85 benchmark circuits show that the proposed method can considerably decrease hardware complexity on average. If the circuit has few primary input and primary output lines, the proposed method is superior when the circuit scale becomes larger.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115309201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Modified ecimation ilter esign for Oversampled Sigma elta A/ Converters 过采样Sigma elta A/转换器的改进消除滤波器设计
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611308
Chen Lei, Zhao Yuan-fu, Gao De-yuan, Wen Wu, Wang Zongmin, Z. Xiaofei, Peng Heping
{"title":"A Modified ecimation ilter esign for Oversampled Sigma elta A/ Converters","authors":"Chen Lei, Zhao Yuan-fu, Gao De-yuan, Wen Wu, Wang Zongmin, Z. Xiaofei, Peng Heping","doi":"10.1109/ICASIC.2005.1611308","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611308","url":null,"abstract":"The paper presents a novel lower power polyphase transformable stage nonrecursive comb (PTSNC) filter architecture considering the area and power consumption, which is very suitable for high-order oversampled sigma delta A/D converters. The proposed decimation filter has 1/3 less hardware and power compared to conventional non-recursive decimation filters when the filter was implemented using 0.6-mum CMOS standard when the circuit work clock was 100MHz","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115351918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator 自顶向下的流水线AES密码实现及其fpga仿真加速器验证
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611270
Jae-Gon Lee, Woong Hwangbo, Seonpil Kim, C. Kyung
{"title":"Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator","authors":"Jae-Gon Lee, Woong Hwangbo, Seonpil Kim, C. Kyung","doi":"10.1109/ICASIC.2005.1611270","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611270","url":null,"abstract":"This paper describes top-down implementation of Rijndael, a new advanced encryption standard (AES), cipher for both encryption and decryption. Pipelined architecture was used to maximize the performance. The design started in the untimed functional level description in C. It was refined to behavioral-level design and finally to RTL design with SystemC. To overcome simulation performance degradation with RTL description, we adopted FPGA-based simulation accelerator in the final stage. To reuse the original test vectors, we introduced proxy module for interconnecting simulation environment with acceleration environment. This hides the presence of simulation accelerator from simulator and makes it possible to reuse test vectors of RTL simulation when simulation accelerator is present","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"342 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115408813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new structure of low-noise CMOS differential amplifier 一种低噪声CMOS差分放大器的新结构
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611337
Wei Lan, Gao Jim, Chen Zhongjian, Ji Lijiu
{"title":"A new structure of low-noise CMOS differential amplifier","authors":"Wei Lan, Gao Jim, Chen Zhongjian, Ji Lijiu","doi":"10.1109/ICASIC.2005.1611337","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611337","url":null,"abstract":"A new structure of low-noise CMOS differential amplifier has been presented in this paper. The structure is mainly based on a load of common-gate MOSFETs with resistances in series at sources (CG-R load), which does not increase complication of the circuit. This structure decreases 1/f noise of the load by a (1 + g/sub m2/R) /sup 2/ coefficient, while keeps the voltage gain high. The simulation result for the given example reveals an average reduction of 90% for load noise at low frequencies, compared with current-mirror load (CM load).","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117159489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit design of an improved approximate squaring function 一种改进的近似平方函数的电路设计
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611512
Zhang Xun, Jin Weiwei, Jin Dong-ming
{"title":"Circuit design of an improved approximate squaring function","authors":"Zhang Xun, Jin Weiwei, Jin Dong-ming","doi":"10.1109/ICASIC.2005.1611512","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611512","url":null,"abstract":"An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"20 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120998187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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