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2005 6th International Conference on ASIC最新文献

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Macromodel of switched-capacitor sigma-delta modulator 开关电容σ - δ调制器的宏观模型
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611498
C. Jianping, Wen Zuoxia, Wei Tongli
{"title":"Macromodel of switched-capacitor sigma-delta modulator","authors":"C. Jianping, Wen Zuoxia, Wei Tongli","doi":"10.1109/ICASIC.2005.1611498","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611498","url":null,"abstract":"This paper presented a set of macromodels in terms of HSPICE-acceptable elements and introduced an approach how to perform time domain simulations of switched-capacitor sigma-delta modulators with these macromodels. The proposed simulation method is validated by comparing the simulation result with the corresponding matlab behavioral simulation result.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116915394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A research on optimum-searching quadratic optimization for very large-scale standard cell placement 超大规模标准单元布局的寻优二次优化研究
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611452
Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Zhuoyuan Li
{"title":"A research on optimum-searching quadratic optimization for very large-scale standard cell placement","authors":"Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Zhuoyuan Li","doi":"10.1109/ICASIC.2005.1611452","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611452","url":null,"abstract":"This paper presents a research on how to find the optimal or near optimal solution in the specific standard cell placement of very large-scale integration (VLSI) designs. The optimization methods currently used are faced with big difficulties in finding better placement result. This paper studies the quadratic optimization that is frequently adopted in this field and analyzes the difficulty it faces. Meanwhile, this paper suggests a very efficient quadratic programming based optimization method. This method employs the tactic of hybrid search based on multi-space search and search space traversing to try to find the optimum or near-optimum of the problem. Experimental results show that this method can make up with the shortcomings of the current quadratic optimization used in placement to a far extent and gains much placement improvement.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114251862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An intuitive implementation of continuous-time Gm-C filter 一个直观的实现连续时间Gm-C滤波器
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611358
Shan Li, Chi Zhang
{"title":"An intuitive implementation of continuous-time Gm-C filter","authors":"Shan Li, Chi Zhang","doi":"10.1109/ICASIC.2005.1611358","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611358","url":null,"abstract":"In this paper, a method of intuitive implementation of continuous-time Gm-C filter based on the transfer function is presented and analyzed. Two different filter topologies are compared, the CMFB performance is considered. A 6th lowpass filter is designed and fabricated to verify the methodology using the 0.18 mum process","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114653714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog constraints extraction based on the signal flow analysis 基于信号流分析的模拟约束提取
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611454
Zhe Zhou, Sheqin Dong, Xianlong Hong, Qingsheng Hao, Song Chen
{"title":"Analog constraints extraction based on the signal flow analysis","authors":"Zhe Zhou, Sheqin Dong, Xianlong Hong, Qingsheng Hao, Song Chen","doi":"10.1109/ICASIC.2005.1611454","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611454","url":null,"abstract":"A novel method for analog constraints extraction is presented. In the proposed approach, analog circuits are represented as bipartite graphs, and then divided into two parts, bias part and signal part, composed of stages with respect to the signal flow analysis. Symmetry constraints are extracted by a graph isomorphism algorithm and so do matching constraints by primitive cell recognition with signal flow analysis. All the constraints are classified according to the critical level analysis by the topological, signal flow analysis and their intrinsic sensitivity. Examples drawn from industrial applications demonstrate the method is very effective and promising","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114874702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Application of DRFM in high frequency ground wave radar DRFM在高频地波雷达中的应用
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611429
Cheng Quan, Shi Zhenhua, D. Peng, He Bolin
{"title":"Application of DRFM in high frequency ground wave radar","authors":"Cheng Quan, Shi Zhenhua, D. Peng, He Bolin","doi":"10.1109/ICASIC.2005.1611429","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611429","url":null,"abstract":"Compared with the traditional analog delay, to conveniently control the time delay of responder of high frequency ground wave radar and obtain duplicate signal with better coherence, the digital radio frequency memory (DRFM) which consists of FIFO is designed to sample the received signal of radar at high speed continuously and simulate the target at any distance. This design is proved to meet the demand of responder of radar well","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125690779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A design of high speed AGTL+ output buffer 高速AGTL+输出缓冲器的设计
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611404
Donglin Wang, Shaoqing Li, Zhenyu Zhao
{"title":"A design of high speed AGTL+ output buffer","authors":"Donglin Wang, Shaoqing Li, Zhenyu Zhao","doi":"10.1109/ICASIC.2005.1611404","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611404","url":null,"abstract":"AGTL+ (assisted Gunning transceiver logic+) signal transmission and interface technology are analyzed in this paper. To resolve the problem on such short high-level duration time in traditional design, we have proposed an auxiliary charged circuit structure. According to what I have analyzed, we design and realize an AGTL+ interface circuit, which is completely compatible with Itanium 2 interface and has high-speed and high noise margin. The operating frequency of circuit reaches to 500MHz by SPICE simulation in the condition of 0.18mum standard CMOS process","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125815654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast and stable force-directed placement with implicit buffer planning 具有隐式缓冲规划的快速稳定的力定向放置
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611438
Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang, H.H. Yang
{"title":"A fast and stable force-directed placement with implicit buffer planning","authors":"Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang, H.H. Yang","doi":"10.1109/ICASIC.2005.1611438","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611438","url":null,"abstract":"As technology advances, the number of required buffers increases significantly and it is desirable to plan buffers at placement stage. This paper studies the approach of planning buffers during analytical placement. First, a fast and stable force-directed placement is introduced, which is averagely 1.71 times as fast as Capo8.8, a state-of-the-art placement tool, with little degradation of wire-length. Then a new model for planning buffers during placement is proposed, which can efficiently ensure the convergence of placement iterations only by modeling buffers implicitly with changed density distribution and modified connectivity weight between drivers and receivers. Also, equivalent candidate positions for buffer insertion are explored to resolve buffer overlaps. Experiments show that compared with previous buffer planning methods, our new approach can achieve greater efficiency as well as quality improvement","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast placement approach for large scale modules based on less flexibility first principles 基于低灵活性第一原则的大型模块快速放置方法
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611443
Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu
{"title":"A fast placement approach for large scale modules based on less flexibility first principles","authors":"Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu","doi":"10.1109/ICASIC.2005.1611443","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611443","url":null,"abstract":"Conventional simulated annealing (SA) based placement could be very time consuming as the design complexity increases. In this paper, we present a new approach for large scale building blocks based on less flexibility first (LFF) principles. Since the resource constraints at the beginning, middle, or end of the packing process varies a lot, we divide the packing process into several continuous stages and apply different heuristic packing strategies which implies the LFF principles. Experiment results show that our approach could generate an optimized placement much quicker than SA based approaches. Also, the placement result could be used as an initial solution for SA-based algorithms. In another experiment, we start such a SA process with lower temperature and get similar solution quality but shorter execution time than SA begins with random initial solutions","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125869661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization technique 3.3 v, 1.9 ghz，采用多段线性化技术的高线性CMOS上混频器
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611336
Zhanguo Xi, Yajie Qin, Zhiliang Hong
{"title":"A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization technique","authors":"Zhanguo Xi, Yajie Qin, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611336","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611336","url":null,"abstract":"This paper presents a single side band up-mixer implemented in SMIC 0.35 mum CMOS technology. It can be used in low-IF direct conversion PCS 1900 (1850-1910MHz) transceiver systems. The mixer is based on multi-tanh linearization technique and achieves high linearity. It operates at a single power supply of 3.3V and consumes only 6mA. The up-mixer with the output buffer achieves an IIP3 of 8dBm and a 1-dB compression point of 0dBm","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124758721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Power property analysis for CMOS integrated circuits CMOS集成电路的功率特性分析
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611486
Yongjun Xu, Chaonong Xu, Xiaowei Li
{"title":"Power property analysis for CMOS integrated circuits","authors":"Yongjun Xu, Chaonong Xu, Xiaowei Li","doi":"10.1109/ICASIC.2005.1611486","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611486","url":null,"abstract":"Power consumption has become one of the primary constraints of integrated circuit designs, especially for wireless communication environments and battery-operated applications. Some important power information is very needed to be known in design phases. In this paper, two parameters of variation and expectation rate (VER) and maximum-skew ratio (MSR) are defined along with expectation and variation to describe the complicated total power behavioral. To achieve accurate analysis of all these power properties, a quantified experimental method is proposed based on the existing dynamic and leakage power models and the results show the analysis environment and the parameters are very useful for low power and high performance circuit system designs","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124991481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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