{"title":"3.3 v, 1.9 ghz,采用多段线性化技术的高线性CMOS上混频器","authors":"Zhanguo Xi, Yajie Qin, Zhiliang Hong","doi":"10.1109/ICASIC.2005.1611336","DOIUrl":null,"url":null,"abstract":"This paper presents a single side band up-mixer implemented in SMIC 0.35 mum CMOS technology. It can be used in low-IF direct conversion PCS 1900 (1850-1910MHz) transceiver systems. The mixer is based on multi-tanh linearization technique and achieves high linearity. It operates at a single power supply of 3.3V and consumes only 6mA. The up-mixer with the output buffer achieves an IIP3 of 8dBm and a 1-dB compression point of 0dBm","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization technique\",\"authors\":\"Zhanguo Xi, Yajie Qin, Zhiliang Hong\",\"doi\":\"10.1109/ICASIC.2005.1611336\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a single side band up-mixer implemented in SMIC 0.35 mum CMOS technology. It can be used in low-IF direct conversion PCS 1900 (1850-1910MHz) transceiver systems. The mixer is based on multi-tanh linearization technique and achieves high linearity. It operates at a single power supply of 3.3V and consumes only 6mA. The up-mixer with the output buffer achieves an IIP3 of 8dBm and a 1-dB compression point of 0dBm\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611336\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
本文介绍了一种采用中芯0.35 μ m CMOS技术实现的单边带上混频器。它可用于低中频直接转换PCS 1900 (1850-1910MHz)收发器系统。混合器采用多段线性化技术,实现了高线性度。它在3.3V的单电源下工作,功耗仅为6mA。带输出缓冲器的上混频器实现了8dBm的IIP3和0dBm的1db压缩点
A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization technique
This paper presents a single side band up-mixer implemented in SMIC 0.35 mum CMOS technology. It can be used in low-IF direct conversion PCS 1900 (1850-1910MHz) transceiver systems. The mixer is based on multi-tanh linearization technique and achieves high linearity. It operates at a single power supply of 3.3V and consumes only 6mA. The up-mixer with the output buffer achieves an IIP3 of 8dBm and a 1-dB compression point of 0dBm