{"title":"具有隐式缓冲规划的快速稳定的力定向放置","authors":"Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang, H.H. Yang","doi":"10.1109/ICASIC.2005.1611438","DOIUrl":null,"url":null,"abstract":"As technology advances, the number of required buffers increases significantly and it is desirable to plan buffers at placement stage. This paper studies the approach of planning buffers during analytical placement. First, a fast and stable force-directed placement is introduced, which is averagely 1.71 times as fast as Capo8.8, a state-of-the-art placement tool, with little degradation of wire-length. Then a new model for planning buffers during placement is proposed, which can efficiently ensure the convergence of placement iterations only by modeling buffers implicitly with changed density distribution and modified connectivity weight between drivers and receivers. Also, equivalent candidate positions for buffer insertion are explored to resolve buffer overlaps. Experiments show that compared with previous buffer planning methods, our new approach can achieve greater efficiency as well as quality improvement","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fast and stable force-directed placement with implicit buffer planning\",\"authors\":\"Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang, H.H. Yang\",\"doi\":\"10.1109/ICASIC.2005.1611438\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As technology advances, the number of required buffers increases significantly and it is desirable to plan buffers at placement stage. This paper studies the approach of planning buffers during analytical placement. First, a fast and stable force-directed placement is introduced, which is averagely 1.71 times as fast as Capo8.8, a state-of-the-art placement tool, with little degradation of wire-length. Then a new model for planning buffers during placement is proposed, which can efficiently ensure the convergence of placement iterations only by modeling buffers implicitly with changed density distribution and modified connectivity weight between drivers and receivers. Also, equivalent candidate positions for buffer insertion are explored to resolve buffer overlaps. Experiments show that compared with previous buffer planning methods, our new approach can achieve greater efficiency as well as quality improvement\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611438\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611438","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast and stable force-directed placement with implicit buffer planning
As technology advances, the number of required buffers increases significantly and it is desirable to plan buffers at placement stage. This paper studies the approach of planning buffers during analytical placement. First, a fast and stable force-directed placement is introduced, which is averagely 1.71 times as fast as Capo8.8, a state-of-the-art placement tool, with little degradation of wire-length. Then a new model for planning buffers during placement is proposed, which can efficiently ensure the convergence of placement iterations only by modeling buffers implicitly with changed density distribution and modified connectivity weight between drivers and receivers. Also, equivalent candidate positions for buffer insertion are explored to resolve buffer overlaps. Experiments show that compared with previous buffer planning methods, our new approach can achieve greater efficiency as well as quality improvement