一种构造自对偶电路的新方法

2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI:10.1109/ICASIC.2005.1611421

Wang Wei, Jianhui Jiang

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引用次数: 4

摘要

本文提出了一种面积效率更高的自对偶电路构造方法。基于ISCAS85基准电路的实验结果表明，该方法可以显著降低硬件复杂度。当电路的一次输入和一次输出线路较少时，当电路规模变大时，所提出的方法更加优越。

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A novel method for the construction of self-dual circuits

This paper presents a more area-effective method to construct self-dual circuits. The experimental results based on ISCAS85 benchmark circuits show that the proposed method can considerably decrease hardware complexity on average. If the circuit has few primary input and primary output lines, the proposed method is superior when the circuit scale becomes larger.

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来源期刊

2005 6th International Conference on ASIC

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