{"title":"一种改进的近似平方函数的电路设计","authors":"Zhang Xun, Jin Weiwei, Jin Dong-ming","doi":"10.1109/ICASIC.2005.1611512","DOIUrl":null,"url":null,"abstract":"An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"20 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Circuit design of an improved approximate squaring function\",\"authors\":\"Zhang Xun, Jin Weiwei, Jin Dong-ming\",\"doi\":\"10.1109/ICASIC.2005.1611512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"20 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Circuit design of an improved approximate squaring function
An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.