Design and implementation of DFT strategy in ASIC design of resilient packet ring

Abstract

According to the practical test requirements of resilient packet ring (RPR) application specific integrated circuit (ASIC), design for testability (DFT) strategy that applies three different DFT methods compositively is proposed in this paper. Principles and key methods used in the strategy are introduced, including scan chain, boundary scan test (BST), memory built-in-self-test (MBIST). Implementation process and results of the DFT strategy are analyzed in detail. DFT circuits implemented in RPR ASIC have reduced the difficulty of test and improved fault coverage a lot. Adopting DFT techniques logically and compositively is very important