{"title":"高速低功耗凸轮的设计","authors":"Canghai Gu, Hefei Zhu, Xiaofang Zhou, Hao Min, Dian Zhou","doi":"10.1109/ICASIC.2005.1611281","DOIUrl":null,"url":null,"abstract":"A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a high-speed low-power CAM\",\"authors\":\"Canghai Gu, Hefei Zhu, Xiaofang Zhou, Hao Min, Dian Zhou\",\"doi\":\"10.1109/ICASIC.2005.1611281\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611281\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文提出了一种低功耗内容可寻址存储器。采用两级比较的方法获得了较好的TLB性能，并在功率模型的基础上提出了最佳的低功耗结构。此外，还采用了较低的电压摆幅来降低功耗。该电路采用0.18 μ m 1P6M CMOS工艺实现。仿真结果表明，在64入口的TLB中，它的功耗仅为4.59 muw/bit，最大延迟为0.983 ns
A low power content addressable memory is presented in this paper. Two-stage comparison is used to get good performance in TLB and the best low power structure is put forward based on the power model. Lower voltage swing is also applied to reduce the power dissipation. This circuit is implemented in 0.18 mum 1P6M CMOS process. Simulation results indicate that it only consumes 4.59 muw/bit with the maximum delay of 0.983 ns in a 64-entry TLB
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