A new FPGA packing algorithm based on the modeling method for logic block

Abstract

Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing