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2005 6th International Conference on ASIC最新文献

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3D placement algorithm considering vertical channels and guided by 2D placement solution 考虑垂直通道并以二维布局方案为导向的三维布局算法
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611446
Guilin Liu, Zhuoyuan Li, Qiang Zhou, Xianlong Hong, Hannah Honghua Yang
{"title":"3D placement algorithm considering vertical channels and guided by 2D placement solution","authors":"Guilin Liu, Zhuoyuan Li, Qiang Zhou, Xianlong Hong, Hannah Honghua Yang","doi":"10.1109/ICASIC.2005.1611446","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611446","url":null,"abstract":"3D integration is a potential solution to solve complex problem caused by interconnect delay that dominates the total budgets. In this placer, we bring up a 3D placement algorithm and focus on two issues: the effect of vertical channels and the constraint that cells can not leave the plane after assigned to it. Firstly, we develop an algorithm to verify the effect of vertical channels in wire length optimization. Secondly, because of the constraint presented above the placement quality is restricted badly. We research the possibility of improving placement quality by importing an initial solution. Experiments on a set of benchmarks prove our algorithm efficient and effective.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Minimum error based affine arithmetic for variational timing analysis 基于最小误差仿射算法的变分时序分析
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611491
Yi Zou, Mengsheng Zhang, Yici Cai, Qiang Zhou, Xianlong Hong
{"title":"Minimum error based affine arithmetic for variational timing analysis","authors":"Yi Zou, Mengsheng Zhang, Yici Cai, Qiang Zhou, Xianlong Hong","doi":"10.1109/ICASIC.2005.1611491","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611491","url":null,"abstract":"In this paper, we describes a novel improvement for affine arithmetic which is widely used in statistical timing analysis and circuit simulation. The representation and calculation method for affine arithmetic is both simple and accurate comparing with previous works. The rule for calculating interval multiplication is simple and effective. It can both give a conservative bound and a minimum error affine approximation at the same time. An application for variational timing analysis demonstrated the usefulness of affine arithmetic","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A mixed-signal driver chip for 65K-color passive-matrix OLED 用于65k色无源矩阵OLED的混合信号驱动芯片
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611361
Wenyu Xiao, Zhiliang Chen
{"title":"A mixed-signal driver chip for 65K-color passive-matrix OLED","authors":"Wenyu Xiao, Zhiliang Chen","doi":"10.1109/ICASIC.2005.1611361","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611361","url":null,"abstract":"Organic light emitting display (OLED) is a new type of flat-panel display (FPD). And the research on the mix-signal driver chip for OLED is still going on. A single-chip passive-matrix OLED driver for 96 (RGB) times 64-pixel panel is presented in this paper. This driver chip has a 256-step contrast control and a 65k-color control. It consists of a digital controller, a SRAM as display data memory, a built-in DC-DC boost converter, an oscillator, 3 (RGB) reference current generators, 64 common drivers, and 96 times 3 segment drivers. The segment drivers use the pulse amplitude modulation (PAM) method to modulate grayscales and the voltage pre-charge technology to pre-charge the OLED pixels. This chip is a typical current-drive circuit. Simulation and analysis of its power consumption indicate that it is necessary for us to research the circuit design of the drivers and display mechanism (including pre-charge and discharge) further","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132418337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel digital soft-start circuit for DC-DC switching regulator 一种新型的DC-DC开关稳压器数字软启动电路
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611391
Lai Xin-quan, Guo Jianping, Yu Weixue, Cao Yu
{"title":"A novel digital soft-start circuit for DC-DC switching regulator","authors":"Lai Xin-quan, Guo Jianping, Yu Weixue, Cao Yu","doi":"10.1109/ICASIC.2005.1611391","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611391","url":null,"abstract":"A new CMOS-compatible digital soft-start circuit for DC-DC switching regulator is presented in this paper, for which the technical is adopted to eliminate the inrush current and avoid the overshoot of the output voltage. It's fully integrated on chip, so that the external soft-start capacitor is not in need, which leads to the reduction of the required board space and component cost. Hspice simulation shows that, while the system has an output voltage of 1.5V at a load of 6A, the envelop of inductor current increases placidly at approximately 1.43A/ms and output voltage increases about 16mV every cycle","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114914964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Bus buffer modeling and optimization for a microprocessor 微处理器总线缓冲区建模与优化
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611284
Xufan Wu, Jun Yang, Longxing Shi
{"title":"Bus buffer modeling and optimization for a microprocessor","authors":"Xufan Wu, Jun Yang, Longxing Shi","doi":"10.1109/ICASIC.2005.1611284","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611284","url":null,"abstract":"Inserting bus buffer is one significant method for solving the collisions in the microprocessor. And it is pivotal to determine the buffer size because of the performance and hardware resource constraints. This paper proposes a method for estimating the buffer size based on a prioritized M/G/1 queuing model and a high-level simulation model according to a RISC microprocessor. Both the results of queuing network model and the results of simulation model were found to be valuable. With the help of proposed simulation and estimating method, bus buffer size can be determined fast and accurately for the implementation","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133776441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deterministic skip lists in analog topological placement 模拟拓扑布局中的确定性跳跃表
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611437
S. C. Maruvada, A. Berkman, K. Krishnamoorthy, F. Balasa
{"title":"Deterministic skip lists in analog topological placement","authors":"S. C. Maruvada, A. Berkman, K. Krishnamoorthy, F. Balasa","doi":"10.1109/ICASIC.2005.1611437","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611437","url":null,"abstract":"This paper presents a novel algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible (S-F) binary tree representations (Balasa et al., 2004) of the layout, the novel approach employs 1-3 deterministic skip lists (Munro et al., 1992) and (Papadakis, 1993), exhibiting running times at least 20-30% better than previous (nonslicing) topological algorithms for analog placement, and significantly better (typically, over 100%) than more traditional approaches based on the absolute representation","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133618175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel ESD protection design methodology and latchup prevention for a 0.5-/spl mu/m CMOS ASIC library 0.5-/spl μ m CMOS专用集成电路库的新型ESD保护设计方法和锁存预防
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611495
Wang Yuan, Jia Song, Chen Zhongjian, Ji Lijiu
{"title":"Novel ESD protection design methodology and latchup prevention for a 0.5-/spl mu/m CMOS ASIC library","authors":"Wang Yuan, Jia Song, Chen Zhongjian, Ji Lijiu","doi":"10.1109/ICASIC.2005.1611495","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611495","url":null,"abstract":"In this paper, instead of the traditional experience-based trial-and-error ESD design approach, a novel ESD protection design methodology is proposed, which resolves the costly and time-consuming problems of high-performance ESD protection development in deep-submicron CMOS technology. And this novel design method is conducted and verified in a 0.5-mum CMOS technology to accomplish I/O cell design of a CMOS ASIC library, whose human-body-model ESD level can be great than 4.5kV. To effectively improve latchup free capability, latchup prevention design is also discussed","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130531729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware-software cosynthesis of multitask MPSoCs with real-time constraints 实时约束下多任务mpsoc的软硬件协同合成
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611458
Choonseung Lee, S. Ha
{"title":"Hardware-software cosynthesis of multitask MPSoCs with real-time constraints","authors":"Choonseung Lee, S. Ha","doi":"10.1109/ICASIC.2005.1611458","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611458","url":null,"abstract":"The cosynthesis problem addressed in this paper involves three subproblems: selection of appropriate processing elements, mapping and scheduling of function blocks to the selected processing elements, and schedulability analysis. We have presented a cosynthesis framework in our earlier work (Oh and Ha, 1999) that defines an iteration loop of three steps that attack the subproblems separately. Despite many good features, our previous technique has a severe restriction that a task monopolizes the entire system once activated. But in general we may obtain higher performance if multiple tasks can be running concurrently on different processor cores. It is the main contribution of this paper that we extend the previous framework to be applicable for general multiprocessor systems with diverse operating policies. We demonstrate the performance improvement from the proposed work with a multi-media real-time application, DVR system, and randomly generated multi-task graphs","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116551442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Implementation of adaptive blind equalizer with carrier recovery for QAM receiver chip QAM接收机芯片载波恢复自适应盲均衡器的实现
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611248
Yongxue Zhang, Lixin Yu
{"title":"Implementation of adaptive blind equalizer with carrier recovery for QAM receiver chip","authors":"Yongxue Zhang, Lixin Yu","doi":"10.1109/ICASIC.2005.1611248","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611248","url":null,"abstract":"In QAM demodulator chip, the blind adaptive decision feedback equalizer and carrier recovery function must be improved. Among existing works of high speed pipelined adaptive DFE (decision feedback equalizer), the time multiplexing architecture based on the MUX control unit is very attractive. It suffers from that complex control unit increases in proportion to filter length. This paper mainly proposes pipeline DFE structure using relaxed look ahead, retiming technology and recirculating register technique result in a substantial hardware saving than the time multiplying architecture based on the MUX control units and parallel processing. Meanwhile, in the carrier recovery loop, combining with Kim's phase detector, by adjusting the loop bandwidth in response to output of phase detector, the convergence time of acquisition and phase jitter in the steady state can be reduced. The scheme, simulated by software simulation, implemented by Virtex-II-3000 FPGA, has been applied to 4,16,32,64,128, 256 QAM modulation, can acquire up to plusmn200KHz offset. The QAM receiver chip is fabricated in SMIC 0.18 micron fabrication process successfully. The whole chip comprises 10bit ADC, PLL, AGC, variable symbol rate recovery, DFE, adaptive carrier recovery and feed forward error controller module, the working frequency is 120MHz","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS RF receiver: from system architecture to circuit implementation CMOS射频接收器:从系统架构到电路实现
2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI: 10.1109/ICASIC.2005.1611238
Pengfei Zhang
{"title":"CMOS RF receiver: from system architecture to circuit implementation","authors":"Pengfei Zhang","doi":"10.1109/ICASIC.2005.1611238","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611238","url":null,"abstract":"RF-CMOS is considered more favorable primarily for the following two reasons: Firstly, capitalizing on the fabrication maturity and manufacture volume, one would justifiably expect the lowest possible cost. Secondly, it has undoubtedly the best potential for wireless system-on-chip (SOC) for its seamless compatibility with digital baseband circuit fabrication process. This paper reviewed system architectures of receiver design with emphasis on suitability of CMOS implementation. Circuit design issues for various building blocks in a typical receiver have been discussed. Finally, a design example of a 5-GHz receiver for WLAN application has been demonstrated","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132742314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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