Implementation of adaptive blind equalizer with carrier recovery for QAM receiver chip

Abstract

In QAM demodulator chip, the blind adaptive decision feedback equalizer and carrier recovery function must be improved. Among existing works of high speed pipelined adaptive DFE (decision feedback equalizer), the time multiplexing architecture based on the MUX control unit is very attractive. It suffers from that complex control unit increases in proportion to filter length. This paper mainly proposes pipeline DFE structure using relaxed look ahead, retiming technology and recirculating register technique result in a substantial hardware saving than the time multiplying architecture based on the MUX control units and parallel processing. Meanwhile, in the carrier recovery loop, combining with Kim's phase detector, by adjusting the loop bandwidth in response to output of phase detector, the convergence time of acquisition and phase jitter in the steady state can be reduced. The scheme, simulated by software simulation, implemented by Virtex-II-3000 FPGA, has been applied to 4,16,32,64,128, 256 QAM modulation, can acquire up to plusmn200KHz offset. The QAM receiver chip is fabricated in SMIC 0.18 micron fabrication process successfully. The whole chip comprises 10bit ADC, PLL, AGC, variable symbol rate recovery, DFE, adaptive carrier recovery and feed forward error controller module, the working frequency is 120MHz