Deterministic skip lists in analog topological placement

Abstract

This paper presents a novel algorithm for device-level analog placement with symmetry constraints. Based on the exploration of symmetric-feasible (S-F) binary tree representations (Balasa et al., 2004) of the layout, the novel approach employs 1-3 deterministic skip lists (Munro et al., 1992) and (Papadakis, 1993), exhibiting running times at least 20-30% better than previous (nonslicing) topological algorithms for analog placement, and significantly better (typically, over 100%) than more traditional approaches based on the absolute representation