A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection

A novel low-swing interface circuit for asynchronous interconnection is proposed in this paper. It takes a level-triggered differential latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the method of driver-array (Fei Qiao et al., 2003) .The proposed circuit consumes less power than previously reported designs and can work up to 500 MHz, which is simulated and fabricated with SMIC 0.18-mum 1.8-V digital CMOS technology