2012 17th IEEE European Test Symposium (ETS)最新文献_第4页

Disturbance fault testing on various NAND flash memories 各种NAND快闪记忆体的干扰故障测试

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233030

Chih-Sheng Hou, Jin-Fu Li

引用次数: 0

Functional analysis of circuits under timing variations 时序变化下电路的功能分析

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233031

M. Dehbashi, G. Fey, K. Roy, A. Raghunathan

引用次数: 2

Increasing autonomous fault-tolerant FPGA-based systems' lifetime 提高基于fpga的自主容错系统的寿命

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233006

C. Bolchini, A. Miele, C. Sandionigi

引用次数: 9

Characterization and handling of low-cost micro-architectural signatures in MPSoCs mpsoc中低成本微架构特征的表征与处理

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233011

Armin Krieg, J. Grinschgl, C. Steger, R. Weiss, Andreas Genser, H. Bock, J. Haid

{"title":"Characterization and handling of low-cost micro-architectural signatures in MPSoCs","authors":"Armin Krieg, J. Grinschgl, C. Steger, R. Weiss, Andreas Genser, H. Bock, J. Haid","doi":"10.1109/ETS.2012.6233011","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233011","url":null,"abstract":"In recent years the wide spread introduction of small embedded systems into every corner of everyday life lead to the strong need for highly reliable and secure computing machines. These machines now affect the safety of humans as well as the security of personal data and consequently money transactions. To ensure the integrity of these systems' operating state, several fault detection mechanisms have been developed to safely correct or stop unforeseen execution behavior. Because of the rise of battery or even field-supplied systems these mechanisms often heavily decrease available power budgets or lead to significantly increased production costs. Therefore, this paper introduces novel micro-architectural execution signature characterization and handling techniques for system-on-chip designs providing power estimation hardware. Existing power sensor infrastructure is reused to enable efficient system-state monitoring using micro-architectural hashes to cover a wide range of implemented system functionality. Reduced hashing implementations are characterized for their fault detection efficiency. This hardware-based approach provides a completely transparent solution to counteract faults resulting from emerging wearout defects or intentional attacks on the execution integrity.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131970589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Testing of digitally assisted adaptive analog/RF systems using tuning knob — Performance space estimation 使用调谐旋钮的数字辅助自适应模拟/射频系统测试。性能空间估计

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233038

A. Banerjee, S. Devarakond, Shreyas Sen, D. Banerjee, A. Chatterjee

{"title":"Testing of digitally assisted adaptive analog/RF systems using tuning knob — Performance space estimation","authors":"A. Banerjee, S. Devarakond, Shreyas Sen, D. Banerjee, A. Chatterjee","doi":"10.1109/ETS.2012.6233038","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233038","url":null,"abstract":"Testing of adaptive analog/RF systems is challenging as any test procedure must ensure that the system adapts correctly to external perturbations (process, workload) without incurring the excessive test time associated with iterative tuning procedures. This problem is made worse by the increased number of adaptation settings (“tuning knob values”) and the requirement of measuring specifications at all of these settings. In this paper, a new test technique is proposed that allows the closed loop performance of the adaptation procedure to be predicted from a set of open-loop tests. The optimal knob settings where the system should be tested in open-loop are found using a gradient based search algorithm and optimized test signals are generated such that the error in performance prediction across different tuning knob settings is minimized. The results of these tests are then mapped to the performance of the adaptive system which is validated implicitly without incurring large testing and tuning costs. Simulation results and hardware measurement results prove the validity of the proposed technique.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133615219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Bandwidth-aware test compression logic for SoC designs 带宽感知测试压缩逻辑的SoC设计

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233003

Jakub Janicki, J. Tyszer, Grzegorz Mrugalski, J. Rajski

引用次数: 21

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands 时分多路复用测试soc与DVS和多个电压岛

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233019

X. Kavousianos, K. Chakrabarty, A. Jain, R. Parekhji

{"title":"Time-division multiplexing for testing SoCs with DVS and multiple voltage islands","authors":"X. Kavousianos, K. Chakrabarty, A. Jain, R. Parekhji","doi":"10.1109/ETS.2012.6233019","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233019","url":null,"abstract":"Dynamic voltage scaling (DVS) has been widely adopted in multicore SoCs for reducing dynamic power consumption. Despite its benefits, the use of DVS increases test time because high product quality can only be ensured by testing every core at multiple supported voltage settings; hence the repetitive application of the same or different tests at multiple voltage settings becomes necessary. In addition, testing at lower supply voltage settings increases considerably the length of each test because lower scan frequencies must be used for shifting test data using scan chains. Standard scheduling techniques fail to reduce the test time for DVS-based SoCs since they do not model testing at multiple voltage settings. In addition, they do not consider the practical aspects of tester overhead and the dependencies between core voltage settings due to the use of voltage islands. To alleviate the detrimental impact of DVS on test application time, we propose a time-division multiplexing (TDM) method and an integer linear programming-based test scheduling technique, which exploit high automatic test equipment (ATE) frequencies even when low shift frequencies must be used at low voltage settings. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling method.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127147032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Power-aware testing: The next stage 功率感知测试:下一个阶段

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233000

X. Wen

引用次数: 1

Dependable embedded systems: The German research foundation DFG priority program SPP 1500 可靠的嵌入式系统:德国研究基金会DFG优先计划spp1500

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233053

J. Henkel, O. Bringmann, A. Herkersdorf, W. Rosenstiel, N. Wehn

引用次数: 0

Funding project DIANA — Integrated diagnostics for the analysis of electronic failures in vehicles 资助项目DIANA——车辆电子故障综合诊断分析

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233050

P. Engelke, H. Obermeir

引用次数: 1