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2012 17th IEEE European Test Symposium (ETS)最新文献

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VLSI Test technology: Why is the field not sexy enough? VLSI测试技术:为什么这个领域不够性感?
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233047
S. Hamdioui, R. Aitken
{"title":"VLSI Test technology: Why is the field not sexy enough?","authors":"S. Hamdioui, R. Aitken","doi":"10.1109/ETS.2012.6233047","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233047","url":null,"abstract":"Although it is an integral part of any manufactured chip and a crucial step to guarantee the required quality, VLSI Test technology seems to become less attractive/interesting for the research community. Funding bodies are minimizing their funding in the area, scientists are moving to other hot topics, industry is not seriously supporting academia in the field, etc.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reducing test cost for mixed signal circuits “From TOETS to ELESIS” 降低混合信号电路的测试成本“从TOETS到ELESIS”
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233051
M. Azimane
{"title":"Reducing test cost for mixed signal circuits “From TOETS to ELESIS”","authors":"M. Azimane","doi":"10.1109/ETS.2012.6233051","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233051","url":null,"abstract":"In the coming years European Semiconductor companies will bring many new applications to the market to improve the way of living in Europe. Examples are linked to road safety, personal health care, secured wireless communications, and lighting and consumer electronics. These applications concern very complex semiconductor systems with highly integrated technologies where digital, memories and analogue are funnelled in one piece of silicon. In these kind of applications, reliability and trustability is a key factor which cannot be guaranteed without extensive test solutions. This may lead to expensive and unreliable test solutions when necessary preventive efforts are omitted. Within the ELESIS project, we have built a European research consortium that provides cooperation between leading semiconductors companies in Europe, small and medium enterprises that are dedicated to system test and tooling and well-recognized European Institutes and Universities. In this European research consortium, we will focus on improving the industrial test infrastructure for mixed signal and analog circuits, leading to safe, reliable, high quality and low cost semiconductors products in Europe, starting from the TOETS consortium partners and experience on digital circuits.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125522043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On-chip delay measurement circuit 片上延迟测量电路
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233014
A. Jain, A. Veggetti, D. Crippa, P. Rolandi
{"title":"On-chip delay measurement circuit","authors":"A. Jain, A. Veggetti, D. Crippa, P. Rolandi","doi":"10.1109/ETS.2012.6233014","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233014","url":null,"abstract":"A novel On-chip delay measurement circuit is presented which is suitable for wide applications involving on-chip measurements, monitoring and process compensation. The circuit is based upon multiple characterization units consisting of ring oscillator, latches and counter. The delay unit used in ring oscillator defines the measurement resolution for the characterization unit. Each characterization unit has different delay cell with delay varying by few Pico-seconds (~1 to 5 picoseconds) with other one, which helps in increasing the resolution. All units give values based on their delay units and collectively all values forms a statistical space whose median gives the pulse width value. In this way, the circuit overcomes the limitations of earlier proposed on-chip measurement systems by offering high accuracy, high resolution and wide range of measurement using very few components. Silicon results on CMOS 40nm technology node for characterization of memory access time based upon proposed system are also presented.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126361437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Exact stuck-at fault classification in presence of unknowns 在未知情况下精确的故障卡滞分类
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233017
Stefan Hillebrecht, M. Kochte, H. Wunderlich, B. Becker
{"title":"Exact stuck-at fault classification in presence of unknowns","authors":"Stefan Hillebrecht, M. Kochte, H. Wunderlich, B. Becker","doi":"10.1109/ETS.2012.6233017","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233017","url":null,"abstract":"Fault simulation is an essential tool in electronic design automation. The accuracy of the computation of fault coverage in classic n-valued simulation algorithms is compromised by unknown (X) values. This results in a pessimistic underestimation of the coverage, and overestimation of unknown (X) values at the primary and pseudo-primary outputs. This work proposes the first stuck-at fault simulation algorithm free of any simulation pessimism in presence of unknowns. The SAT-based algorithm exactly classifies any fault and distinguishes between definite and possible detects. The pessimism w.r.t. unknowns present in classic algorithms is discussed in the experimental results on ISCAS benchmark and industrial circuits. The applicability of our algorithm to large industrial circuits is demonstrated.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125665792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Adaptive testing: Conquering process variations 适应性测试:克服过程变化
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233045
E. Yilmaz, S. Ozev, O. Sinanoglu, P. Maxwell
{"title":"Adaptive testing: Conquering process variations","authors":"E. Yilmaz, S. Ozev, O. Sinanoglu, P. Maxwell","doi":"10.1109/ETS.2012.6233045","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233045","url":null,"abstract":"Increasing process variations result in increasing statistical diversity in manufactured devices. Test plans that are developed without this diversity in mind are bound to result in poor test quality/yield and/or long test times. Adaptive testing is a general term that is used to tailor the test strategy to accommodate a wide range of variation in the statistical characteristics of manufactured devices. In this paper, we provide a review of the key works in both digital and analog domains.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128816468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Defect analysis in power mode control logic of low-power SRAMs 低功耗sram功率模式控制逻辑缺陷分析
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233033
L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine
{"title":"Defect analysis in power mode control logic of low-power SRAMs","authors":"L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine","doi":"10.1109/ETS.2012.6233033","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233033","url":null,"abstract":"Summary form only given. Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Indirect method for random jitter measurement on SoCs using critical path characterization 基于关键路径表征的soc随机抖动间接测量方法
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233022
Jae Wook Lee, J. Chun, J. Abraham
{"title":"Indirect method for random jitter measurement on SoCs using critical path characterization","authors":"Jae Wook Lee, J. Chun, J. Abraham","doi":"10.1109/ETS.2012.6233022","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233022","url":null,"abstract":"This paper presents a new method for random jitter measurement on systems-on-a-chip (SoCs) by exploiting shmoo plotting in automatic test equipment (ATE). After finding the maximum operating frequency of a microprocessor using functional test patterns that can sensitize its critical paths, the proposed method constructs a cumulative distribution function (CDF) whose standard deviation represents the root mean square (RMS) value of the random jitter of the clock signals used in the microprocessor. By leveraging tester period resolution with a frequency multiplying phase-locked loop (PLL) in the SoC, the shmoo plot with a fine period step size can detect the jitter component in the clock signal, which reflects the actual jitter that most critical paths undergo. The proposed idea was verified with circuit-level simulations, and was validated by silicon measurements using one of the latest SoC products.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"9 27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129295200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-conditional SAT-ATPG for power-droop testing 多条件SAT-ATPG功率下降测试
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233026
A. Czutro, M. Sauer, I. Polian, B. Becker
{"title":"Multi-conditional SAT-ATPG for power-droop testing","authors":"A. Czutro, M. Sauer, I. Polian, B. Becker","doi":"10.1109/ETS.2012.6233026","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233026","url":null,"abstract":"Power droop is a non-trivial signal-integrity-related effect triggered by specific power-supply conditions. High-frequency and low-frequency power droop may lead to failure of an IC during application time, but they usually remain undetected by state-of-the-art manufacturing test methods, as the fault excitation imposes particular conditions on global switching activity over several time frames. Hence, ATPG for power-droop test (PD-ATPG) is an extremely hard problem that has not yet been solved optimally. In this paper, we use a SAT-based ATPG engine that employs a mechanism known as SAT-solving with qualitative preferences to generate a solution guaranteed to be optimal for a given set of optimisation criteria, however at the expense of high SAT-solving times. Therefore, a well-balanced set of criteria has to be chosen for the SAT-formulation in order to get as good solutions as possible without rendering the SAT-instances impracticably hard. We explore several strategies and evaluate them experimentally.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123023642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
The impact of functional safety standards in the design and test of reliable and available integrated circuits 功能安全标准对设计和测试可靠和可用的集成电路的影响
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233048
R. Mariani
{"title":"The impact of functional safety standards in the design and test of reliable and available integrated circuits","authors":"R. Mariani","doi":"10.1109/ETS.2012.6233048","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233048","url":null,"abstract":"The panel gives an overview of requirements, problems and solutions related to the application of ISO 26262 (the international norm ruling functional safety for automotive) and IEC 61508 2nd edition (the international norm widely used in industrial domain) to the design and test of integrated circuits.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132817352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Memory reliability improvements based on maximized error-correcting codes 基于最大纠错码的内存可靠性改进
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233018
V. Gherman, S. Evain, Y. Bonhomme
{"title":"Memory reliability improvements based on maximized error-correcting codes","authors":"V. Gherman, S. Evain, Y. Bonhomme","doi":"10.1109/ETS.2012.6233018","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233018","url":null,"abstract":"Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some of the most used ECCs. A method is proposed for the selection of multiple-bit errors which can become correctable with a minimal impact on decoder latency. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are equally probable. It is shown that the application of the proposed methods to standard double-bit ECCs can improve the mean-time-to-failure (MTTF) of memories with up to 100%.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115395021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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