低功耗sram功率模式控制逻辑缺陷分析

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI:10.1109/ETS.2012.6233033

L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine

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引用次数: 3

摘要

只提供摘要形式。低功耗sram嵌入功率门控机制，以减少静态功耗。功率门控应用于sram中，使用功率开关来控制施加到各种存储块(阵列，解码器，I/O逻辑等)的电源电压。本文基于电学仿真详细分析了电阻性开路缺陷对产生功率开关控制信号的功率模式控制逻辑的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Defect analysis in power mode control logic of low-power SRAMs

Summary form only given. Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches.

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2012 17th IEEE European Test Symposium (ETS)

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