{"title":"Cost and power efficient timing error tolerance in flip-flop based microprocessor cores","authors":"Stefanos Valadimas, Y. Tsiatouhas, A. Arapoyanni","doi":"10.1109/ETS.2012.6233002","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233002","url":null,"abstract":"Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide timing error tolerance. The proposed and the well known Razor techniques were applied separately in the design of two versions of a 32-bit MIPS microprocessor core using a 90nm CMOS technology. Comparisons based on the experimental results validate the efficiency of the new design approach.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115878749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Functional test generation for hard to detect stuck-at faults using RTL model checking","authors":"M. Prabhu, J. Abraham","doi":"10.1109/ETS.2012.6233016","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233016","url":null,"abstract":"At-speed functional testing has proven to be very effective at uncovering defective chips. However for processor testing, generating instruction level tests for covering all faults is a challenge given the issue of scalability. Data-path faults are relatively easier to control and observe compared to control-path faults. In this paper we present a novel method to generate instruction level tests for hard to detect control-path faults in a processor. We initially map the gate level stuck-at fault to the Register Transfer Level (RTL) and build an equivalent faulty RTL model. The fault activation and propagation constraints are captured using Control and Data Flow Graph of RTL as an Liner Temporal Logic (LTL) property. This LTL property is then negated and given to a Bounded Model Checker based on a Bit-Vector Satisfiability Module Theories (SMT) solver. From the counter-example to the property we can extract a sequence of instructions that activates the gate level fault and propagates the fault effect to one of the observable points in the design. Our approach is completely automatic and does not require any external information or manual intervention. Experimental results show that our method is robust and scalable for generating functional tests for hard to detect faults.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123233463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"OBT for settling error test of sampled-data systems using signal-dependent clocking","authors":"Manuel J. Barragan Asian, G. Léger, J. Huertas","doi":"10.1109/ETS.2012.6233013","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233013","url":null,"abstract":"This work presents a modification of traditional Oscillation-Based Test schemes for sampled-data systems. This new test scheme is based on doubling the sampling frequency when the oscillation changes its sign. This way, the DC level of the output oscillation signal becomes a simple signature sensitive to the settling errors in the device under test and to its oscillation features. The proposed technique is illustrated on a switched-capacitor second-order lowpass filter. This case study is used to show the sensitivity of the proposed signature to the linearity of the DUT. Electrical simulation results are provided to validate the proposal.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130340634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Wang, A. Wallin, V. Izosimov, Urban Ingelsson, Zebo Peng
{"title":"Test tool qualification through fault injection","authors":"Q. Wang, A. Wallin, V. Izosimov, Urban Ingelsson, Zebo Peng","doi":"10.1109/ETS.2012.6233042","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233042","url":null,"abstract":"According to ISO 26262, a recent automotive functional safety standard, verification tools shall undergo qualification, e.g. to ensure that they do not fail to detect faults that can lead to violation of functional safety requirements. We present a semi-automatic qualification method involving a monitor and fault injection that reduce cost in the qualification process. We experiment on a verification tool implemented in LabVIEW.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132434809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault-Tolerant Algebraic Architecture for radiation induced soft-errors","authors":"F. Itturriet, R. Ferreira, L. Carro","doi":"10.1109/ETS.2012.6233040","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233040","url":null,"abstract":"Summary form only given. A novel fault-tolerant microprocessor capable of detecting and correcting radiation-induced soft errors is proposed and evaluated. The Fault-Tolerant Algebraic Architecture (FTAA) performs time redundancy intrinsically with computation, guaranteeing on-the-fly detection and correction of errors disrupting data and logic with minimum overhead. We evaluate the FTAA microprocessor in terms of performance, area, energy consumption, and fault coverage by performing an extensive design space exploration of the architecture.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125936317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A robust metric for screening outliers from analogue product manufacturing tests responses","authors":"Shaji Krishnan, H. Kerkhoff","doi":"10.1109/ETS.2011.31","DOIUrl":"https://doi.org/10.1109/ETS.2011.31","url":null,"abstract":"Mahalanobis distance is one of the commonly used multivariate metrics for finely segregating defective devices from non-defective ones. An associated problem with this approach is the estimation of a robust mean and a covariance matrix. In the absence of such robust estimates, especially in the presence of outliers to test-response measurements, and only a sub-sample from the population is available, the distance metric becomes unreliable. To circumvent this problem, multiple Mahalanobis distances are calculated from selected sets of test-response measurements. They are then suitably formulated to derive a metric that has a reduced variance and robust to shifts or deviations in measurements. In this paper, such a formulation is proposed to qualitatively screen product outliers and quantitatively measure the reliability of the non-defective ones. The application of method is exemplified over a test set of an industrial automobile product.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126703359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}