2012 17th IEEE European Test Symposium (ETS)最新文献_第5页

Multi-voltage aware resistive open fault modeling 多电压感知电阻性开路故障建模

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233021

M. T. Mohammadat, N. Ali, F. Hussin

引用次数: 1

Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation 使用主动细粒度动态运行时自适应减少嵌入式处理器的损耗

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233012

Fabian Oboril, M. Tahoori

引用次数: 16

Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information 结合邻域信息的模拟/混合信号电路的自适应多站点测试

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233010

E. Yilmaz, S. Ozev

引用次数: 8

Through-Silicon-Via resistive-open defect analysis 通硅通阻开路缺陷分析

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233037

C. Metzler, A. Todri, A. Bosio, L. Dilillo, P. Girard, A. Virazel

引用次数: 13

On the detection of path delay faults by functional broadside tests 基于功能侧测试的路径延迟故障检测

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233015

I. Pomeranz

引用次数: 9

On the quality of test vectors for post-silicon characterization 后硅表征测试载体的质量问题

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233027

M. Sauer, A. Czutro, B. Becker, I. Polian

{"title":"On the quality of test vectors for post-silicon characterization","authors":"M. Sauer, A. Czutro, B. Becker, I. Polian","doi":"10.1109/ETS.2012.6233027","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233027","url":null,"abstract":"Post-silicon validation, i.e., physical characterization of a small number of fabricated circuit instances before start of high-volume manufacturing, has become an essential step in integrated circuit production. Post-silicon validation is required to identify intricate logic or electrical bugs which could not be found during pre-silicon verification. In addition, physical characterization is useful to determine the performance distribution of the manufactured circuit instances and to derive performance yield. Test vectors used for this step are subject to different requirements compared to vectors for simulation-based verification or for manufacturing test. In particular, they must sensitize a very comprehensive set of paths in the circuit, assuming massive variations and possible modeling deficiencies. An inadequate test vector set may result in overly optimistic yield estimates and wrong manufacturing decisions. On the other hand, the size of the test vector set is less important than in verification or manufacturing test. In this paper, we systematically investigate the relationship between the quality of the employed test vectors and the accuracy of yield-performance predictions. We use a highly efficient SAT-based algorithm to generate comprehensive test vector sets based on simple model assumptions and validate these test sets using simulated circuit instances which incorporate effects of process variations. The obtained vector sets can also serve as a basis for adaptive manufacturing test.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126367360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

On-line software-based self-test of the Address Calculation Unit in RISC processors RISC处理器中地址计算单元的在线软件自测

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233004

P. Bernardi, Lyl M. Ciganda Brasca, M. D. Carvalho, M. Grosso, Jorge Luis Lagos-Benites, E. Sánchez, M. Reorda, O. Ballan

引用次数: 31

On-chip test comparison for protecting confidential data in secure ICs 在安全集成电路中保护机密数据的片上测试比较

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233039

Jean DaRolt, G. D. Natale, M. Flottes, B. Rouzeyre

引用次数: 8

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs 多位/级流水线adc的增强简化代码线性度测试技术

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233009

Asma Laraba, H. Stratigopoulos, S. Mir, Hervé Naudet, Christophe Forel

引用次数: 12

Fault tolerant FPGA processor based on runtime reconfigurable modules 基于运行时可重构模块的容错FPGA处理器

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233007

M. Psarakis, A. Apostolakis

{"title":"Fault tolerant FPGA processor based on runtime reconfigurable modules","authors":"M. Psarakis, A. Apostolakis","doi":"10.1109/ETS.2012.6233007","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233007","url":null,"abstract":"The increasing use of field programmable devices for the implementation of embedded processors and systems-on-chip even in mission-critical applications demands for fault tolerant techniques to improve reliability and extend system lifetime. Furthermore, the runtime partial reconfiguration potentials of the latest FPGA devices along with the availability of unused programmable resources in most FPGA designs provide interesting opportunities to build fault tolerant mechanisms. In this paper, we exploit the latest dynamic reconfiguration advances and propose a fault-tolerant FPGA processor architecture based on runtime reconfigurable modules. We partition the processor core into reconfigurable modules and duplicate these modules to implement a concurrent error detection mechanism. For every duplicated module we generate precompiled configurations which include spare resources and are used to runtime repair the defective module. The processor freezes upon the detection of an error and an on-chip controller coordinates the processor recovery and repair in a reconfiguration process transparent to the processor. We demonstrate the proposed approach in OpenRISC core, a widely-used open-source soft processor.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124929472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35