2012 17th IEEE European Test Symposium (ETS)最新文献_第2页

Re-using chip level DFT at board level 在板级重用芯片级DFT

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233049

Xinli Gu, J. Rearick, B. Eklow, Martin Keim, J. Qian, A. Jutman, K. Chakrabarty, E. Larsson

引用次数: 0

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test 内置自诊断利用强诊断窗口在混合模式测试

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233025

A. Cook, S. Hellebrand, H. Wunderlich

{"title":"Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test","authors":"A. Cook, S. Hellebrand, H. Wunderlich","doi":"10.1109/ETS.2012.6233025","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233025","url":null,"abstract":"Efficient diagnosis procedures are crucial both for volume and for in-field diagnosis. In either case the underlying test strategy should provide a high coverage of realistic fault mechanisms and support a low-cost implementation. Built-in self-diagnosis (BISD) is a promising solution, if the diagnosis procedure is fully in line with the test flow. However, most known BISD schemes require multiple test runs or modifications of the standard scan-based test infrastructure. Some recent schemes circumvent these problems, but they focus on deterministic patterns to limit the storage requirements for diagnostic data. Thus, they cannot exploit the benefits of a mixed-mode test such as high coverage of non-target faults and reduced test data storage. This paper proposes a BISD scheme using mixed-mode patterns and partitioning the test sequence into “weak” and “strong” diagnostic windows, which are treated differently during diagnosis. As the experimental results show, this improves the coverage of non-target faults and enhances the diagnostic resolution compared to state-of-the-art approaches. At the same time the overall storage overhead for input and response data is considerably reduced.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Embedded synthetic instruments for Board-Level testing 用于板级测试的嵌入式合成仪器

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233044

A. Jutman, S. Devadze, I. Aleksejev, T. Wenzel

引用次数: 5

Online detection and recovery of transient errors in front-end structures of microprocessors 微处理器前端结构瞬态错误的在线检测与恢复

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233041

S. Z. Shazli, M. Tahoori

引用次数: 0

Efficient system-level aging prediction 高效的系统级老化预测

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233028

N. Hatami, R. Baranowski, P. Prinetto, H. Wunderlich

{"title":"Efficient system-level aging prediction","authors":"N. Hatami, R. Baranowski, P. Prinetto, H. Wunderlich","doi":"10.1109/ETS.2012.6233028","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233028","url":null,"abstract":"Non-functional properties (NFPs) of integrated circuits include reliability, vulnerability, power consumption or heat dissipation. Accurate NFP prediction over long periods of system operation poses a great challenge due to prohibitive simulation costs. For instance, in case of aging estimation, the existing low-level models are accurate but not efficient enough for simulation of complex designs. On the other hand, existing techniques for fast high-level simulation do not provide enough details for NFP analysis. The goal of this paper is to bridge this gap by combining the accuracy of low-level models with high-level simulation speed. We introduce an efficient mixed-level NFP prediction methodology that considers both the structure and application of a system. The system is modeled at transaction-level to enable high simulation speed. To maintain accuracy, NFP assessment for cores under analysis is conducted at gate-level by cycle-accurate simulation. We propose effective techniques for cross-level synchronization and idle simulation speed-up. As an example, we apply the technique to analyze aging caused by Negative Bias Temperature Instability in order to identify reliability hot spots. As case studies, several applications on an SoC platform are analyzed. Compared to conventional approaches, the proposed method is from 7 up to 400 times faster with mean error below 0.006%.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124559088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Fast error detection through efficient use of hardwired resources in FPGAs 通过有效地利用fpga中的硬连线资源来快速检测错误

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233005

G. Nazar, L. Carro

引用次数: 14

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates 介绍以缺陷为导向的细胞感知测试方法，以显著降低DPPM率

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233046

F. Hapke, J. Schlöffel

引用次数: 39

DfT support for launch and capture power reduction in launch-off-capture testing DfT支持在发射-捕获测试中降低发射和捕获功率

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233001

S. Saeed, O. Sinanoglu

{"title":"DfT support for launch and capture power reduction in launch-off-capture testing","authors":"S. Saeed, O. Sinanoglu","doi":"10.1109/ETS.2012.6233001","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233001","url":null,"abstract":"At-speed or even faster-than-at-speed testing of VLSI circuits aim at a high quality screening of VLSI circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable to lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose DfT support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner. The DfT support we outline in this paper enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design flow compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering launch/capture power.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Enhanced wafer matching heuristics for 3-D ICs 三维集成电路晶圆匹配启发式改进

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233032

V. Pavlidis, Hu Xu, G. Micheli

引用次数: 0

Impact of NBTI on analog components NBTI对模拟元件的影响

2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233036

Zhengliang Lv, L. Milor, Shiyuan Yang

引用次数: 1