Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates

Abstract

This tutorial will give an introduction to a new defect-oriented test method called cell-aware. This new cell-aware method takes the layout of standard library cells into account when creating the cell-aware ATPG library view. The tutorial will cover the whole cell-aware library characterization flow consisting of a layout extraction step, an analog fault simulation step of all cell-internal bridges and opens and the cell-aware synthesis step to create the new cell-aware ATPG library views, which finally can be used in a normal chip design flow to generate production test patterns. These cell-aware production test patterns have a significantly higher quality than state-of-the-art patterns. Finally, production test results from several hundred thousand tested IC's are presented showing significant reduction of DPPM rates.