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2012 17th IEEE European Test Symposium (ETS)最新文献

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Coupling-based resistive-open defects in TAS-MRAM architectures TAS-MRAM结构中基于耦合的阻性开放缺陷
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233034
Joao Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G. Prenat, J. Alvarez-Herault, K. Mackay
{"title":"Coupling-based resistive-open defects in TAS-MRAM architectures","authors":"Joao Azevedo, A. Virazel, A. Bosio, L. Dilillo, P. Girard, A. Todri, G. Prenat, J. Alvarez-Herault, K. Mackay","doi":"10.1109/ETS.2012.6233034","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233034","url":null,"abstract":"Thermally Assisted Switching Magnetic Random Access Memory (TAS-MRAM) is an emerging technology that offers several advantages compared to existing non-volatile memory technologies. In this paper we show how coupling faults induced by resistive-open defects impact the TAS-MRAM architecture. Results shows that read and write operations may be affected these defects and may induce single and double cell faulty behaviors.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130292819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Diagnostic system based on support-vector machines for board-level functional diagnosis 基于支持向量机的板级功能诊断系统
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233029
Zhaobo Zhang, Xinli Gu, Yaohui Xie, Zhiyuan Wang, Zhanglei Wang, K. Chakrabarty
{"title":"Diagnostic system based on support-vector machines for board-level functional diagnosis","authors":"Zhaobo Zhang, Xinli Gu, Yaohui Xie, Zhiyuan Wang, Zhanglei Wang, K. Chakrabarty","doi":"10.1109/ETS.2012.6233029","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233029","url":null,"abstract":"Fault diagnosis is critical for improving product yield and reducing manufacturing cost. However, it is very challenging to identify the root cause of failures on a complex circuit board. Ambiguous diagnosis results lead to long debug times and even wrong repair actions, which significantly increases the repair cost. We propose an automatic diagnostic system using support vector machines (SVMs). The proposed system acquires debug knowledge from empirical data; this strategy avoids the difficulties involved in knowledge acquisition in traditional fault diagnosis methods. SVMs provide an optimal separating hyperplane in classification. The optimal solution and generalization ability of SVMs lead to higher diagnostic accuracy, compared to the classical learning approaches such as artificial neural networks (ANNs). An industrial board is used to validate the effectiveness of the proposed system. Extensive simulation results demonstrate that the SVMs-based diagnostic system provides quantifiable improvement over current diagnostic software and an ANN-based diagnostic system.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127877075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Adaptive testing of chips with varying distributions of unknown response bits 具有不同未知响应位分布的芯片的自适应测试
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233023
Chandra K. H. Suresh, O. Sinanoglu, S. Ozev
{"title":"Adaptive testing of chips with varying distributions of unknown response bits","authors":"Chandra K. H. Suresh, O. Sinanoglu, S. Ozev","doi":"10.1109/ETS.2012.6233023","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233023","url":null,"abstract":"Traditionally, test patterns that are generated for a given circuit are applied in an identical manner to all manufactured devices. With increasing process variations, the statistical diversity of manufactured devices is increasing, making such one-size-fits-all approaches increasingly inefficient, and resulting in yield and quality loss. Adaptive test techniques address this problem by tailoring the test decisions for the statistical characteristics of the device under test. In this paper, we present several adaptive strategies to enable adaptive unknown bit masking so as to ensure no yield loss while attaining the maximum test quality based on tester memory constraints.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132544100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design FP7合作研究项目DIAMOND:可靠系统设计的诊断、错误建模和校正
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233052
J. Raik
{"title":"FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design","authors":"J. Raik","doi":"10.1109/ETS.2012.6233052","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233052","url":null,"abstract":"DIAMOND project is set to cut development costs for Europe's nanoelectronics industry by simplifying error diagnosis and correction in systems. The project reaches beyond current state-of-the-art by taking an integrated approach to localization and correction of different kinds of errors at various levels. In particular, DIAMOND has a focus on automated design error debug, soft error analysis and post-silicon in situ debug fields. The aim is to provide a holistic, systematic methodology and an integrated environment for diagnosis and correction of different types of errors. The DIAMOND consortium includes universities from Estonia, Sweden, Germany and Austria as well as large companies like IBM, Ericsson and two SMEs TransEDA and Testonica Lab. Here, we summarize the main achievements of the project so far.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121592103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale 介绍MEDIAN:纳米尺度上可制造和可靠的多核架构的新成本行动
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233054
M. Ottavi
{"title":"Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale","authors":"M. Ottavi","doi":"10.1109/ETS.2012.6233054","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233054","url":null,"abstract":"The MEDIAN (ManufacturablE and Dependable multI-core Architectures at Nanoscale) project is a EU funded COST Action aimed at creating a European network of competence and experts on all dependability aspects of future digital systems development, promoting collaboration between industry and research.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114115603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-chip temperature and voltage measurement for field testing 用于现场测试的片上温度和电压测量
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233035
Y. Miura, Yasuo Sato, Yousuke Miyake, S. Kajihara
{"title":"On-chip temperature and voltage measurement for field testing","authors":"Y. Miura, Yasuo Sato, Yousuke Miyake, S. Kajihara","doi":"10.1109/ETS.2012.6233035","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233035","url":null,"abstract":"This paper proposes a novel technique to measure temperature and voltage on-chip in field test. It consists of three types of NBTI-tolerant ring oscillator and counters constructed with a standard cell library. Temperature and voltage are estimated with high accuracy and in a short time.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127071910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Software-Based Self-Test methodology for on-line testing of data TLBs 基于软件的数据tlb在线自测方法
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233043
G. Theodorou, Serafeim Chatzopoulos, N. Kranitis, A. Paschalis, D. Gizopoulos
{"title":"A Software-Based Self-Test methodology for on-line testing of data TLBs","authors":"G. Theodorou, Serafeim Chatzopoulos, N. Kranitis, A. Paschalis, D. Gizopoulos","doi":"10.1109/ETS.2012.6233043","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233043","url":null,"abstract":"For small memory arrays that usually lack Memory Built-In Self-Test (MBIST), such as Translation Lookaside Buffer (TLB) arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for on-line testing of data TLB (D-TLB), both for data (SRAM) and tag (CAM) memory arrays. The SBST methodology exploits existing special purpose instructions that modern ISAs implement to access the TLBs for debug-diagnostic purposes, termed hereafter Direct TLB Access (DTA) instructions, as well as, the trap handler mechanism.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132761664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Combining dynamic slicing and mutation operators for ESL correction 结合动态切片和变异算子进行ESL校正
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233020
Urmas Repinski, Hanno Hantson, M. Jenihhin, J. Raik, R. Ubar, G. D. Guglielmo, G. Pravadelli, F. Fummi
{"title":"Combining dynamic slicing and mutation operators for ESL correction","authors":"Urmas Repinski, Hanno Hantson, M. Jenihhin, J. Raik, R. Ubar, G. D. Guglielmo, G. Pravadelli, F. Fummi","doi":"10.1109/ETS.2012.6233020","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233020","url":null,"abstract":"Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115306907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Toggle-masking scheme for x-filtering x滤波的切换屏蔽方案
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233024
Abishek Ramdas, O. Sinanoglu
{"title":"Toggle-masking scheme for x-filtering","authors":"Abishek Ramdas, O. Sinanoglu","doi":"10.1109/ETS.2012.6233024","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233024","url":null,"abstract":"High quality screening of chips may require aggressive solutions such as faster-than-at-speed testing, which may generate responses with high density of unknown x's. Recently, we proposed a toggle-masking approach capable of masking all the unknown x's and minimizing the over-masked known bits for clustered distribution of unknown bits. In this work, we utilize our toggle-masking framework as a foundation, and transform this solution into an x-filter that allows a certain number/distribution of x's to pass, in order to further improve the observability levels. Naturally, the modified toggle-masking scheme is to be paired with another technique, such as an x-canceling MISR, which is capable of canceling the x's in the signature via post-processing operations. We propose different flavors of the proposed x-filter to be utilized with different versions of x-canceling MISR, which may suffer from test time increase and/or observability loss with high x-density responses. By proposing an x-filter that can adjust the number/distribution of x in-flow into the MISR, a perfect control over test time and observability is delivered, offering a wide spectrum of tradeoff solutions for the designers.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":" 58","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120834654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
BIST design for analog cell matching BIST模拟小区匹配设计
2012 17th IEEE European Test Symposium (ETS) Pub Date : 2012-05-28 DOI: 10.1109/ETS.2012.6233008
C. Duarte, Henrique Cavadas, Pedro Coke, Luis Malheiro, V. Tavares, P. Oliveira
{"title":"BIST design for analog cell matching","authors":"C. Duarte, Henrique Cavadas, Pedro Coke, Luis Malheiro, V. Tavares, P. Oliveira","doi":"10.1109/ETS.2012.6233008","DOIUrl":"https://doi.org/10.1109/ETS.2012.6233008","url":null,"abstract":"This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115999984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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