Adaptive testing of chips with varying distributions of unknown response bits

Abstract

Traditionally, test patterns that are generated for a given circuit are applied in an identical manner to all manufactured devices. With increasing process variations, the statistical diversity of manufactured devices is increasing, making such one-size-fits-all approaches increasingly inefficient, and resulting in yield and quality loss. Adaptive test techniques address this problem by tailoring the test decisions for the statistical characteristics of the device under test. In this paper, we present several adaptive strategies to enable adaptive unknown bit masking so as to ensure no yield loss while attaining the maximum test quality based on tester memory constraints.