C. Duarte, Henrique Cavadas, Pedro Coke, Luis Malheiro, V. Tavares, P. Oliveira
{"title":"BIST design for analog cell matching","authors":"C. Duarte, Henrique Cavadas, Pedro Coke, Luis Malheiro, V. Tavares, P. Oliveira","doi":"10.1109/ETS.2012.6233008","DOIUrl":null,"url":null,"abstract":"This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.","PeriodicalId":429839,"journal":{"name":"2012 17th IEEE European Test Symposium (ETS)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 17th IEEE European Test Symposium (ETS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ETS.2012.6233008","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.