Enhanced wafer matching heuristics for 3-D ICs

Abstract

Summary form only given. Pre-bond test has been identified as a vital step for the wafer level integration of 3-D ICs. The data obtained during this step can guide the subsequent manufacturing stages to improve the functional or parametric yield of the 3-D stack. The existing methods, however, do not relate directly the performance of the resulting circuits with sales revenues. More importantly, methods that consider the distribution of speed of the assembled 3-D stacks neglect the partition of the critical path delay across the layers of the stack. In other words, a physical layer that does not include any critical path does not primarily determine the performance of the system. Consequently, for a method that aims at maximizing the profit that can be made from a 3-D system, this layer should be treated differently.