Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

Dynamic voltage scaling (DVS) has been widely adopted in multicore SoCs for reducing dynamic power consumption. Despite its benefits, the use of DVS increases test time because high product quality can only be ensured by testing every core at multiple supported voltage settings; hence the repetitive application of the same or different tests at multiple voltage settings becomes necessary. In addition, testing at lower supply voltage settings increases considerably the length of each test because lower scan frequencies must be used for shifting test data using scan chains. Standard scheduling techniques fail to reduce the test time for DVS-based SoCs since they do not model testing at multiple voltage settings. In addition, they do not consider the practical aspects of tester overhead and the dependencies between core voltage settings due to the use of voltage islands. To alleviate the detrimental impact of DVS on test application time, we propose a time-division multiplexing (TDM) method and an integer linear programming-based test scheduling technique, which exploit high automatic test equipment (ATE) frequencies even when low shift frequencies must be used at low voltage settings. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling method.