带宽感知测试压缩逻辑的SoC设计

Jakub Janicki, J. Tyszer, Grzegorz Mrugalski, J. Rajski
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引用次数: 21

摘要

本文提出了增强SoC设计测试压缩解决方案的新方法。通过在基于edc的解压缩器中适当地选择或布局ATE通道注入器,所提出的方案能够提高编码效率、测试压缩和测试时间。新技术在测试带宽管理方面的有效性通过在几个工业SoC设计上运行实验来证明,并在此报告。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Bandwidth-aware test compression logic for SoC designs
This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.
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