1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献_第3页

Chip scale packaging for memory devices 存储设备的芯片级封装

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678737

Y. Akiyama, A. Nishimura, I. Anjoh

引用次数: 4

Electrical modeling of the chip scale BGA 芯片级BGA的电学建模

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678906

M. Caggiano, R. Brush, J. Kleban, P. J. Chuaypradit

引用次数: 8

The implications of roadmapping on university research 道路制图对大学研究的影响

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678763

R. Gedney, J. McElroy, P.E. Winkler

{"title":"The implications of roadmapping on university research","authors":"R. Gedney, J. McElroy, P.E. Winkler","doi":"10.1109/ECTC.1998.678763","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678763","url":null,"abstract":"Until 4-5 years ago, technology roadmaps or \"strategies\" were carried out by individual large corporations and considered confidential within each company. Their influence on the industry was dependent on the buying power of the individual corporation. Since 1994, many large OEMs have been willing to share data which has made industry-wide roadmaps feasible. Recently, roadmapping has been carried out by consortia or trade groups such as the SIA, Sematech, IPC and NEMI. The content of the roadmaps is provided by the applicable industry segment experts and provides their collective view of future requirements. The roadmaps have had a profound effect on the way government agencies budget their funds and in turn, on university research: first, because university research is often funded by the government; second because industry, as both funders and receivers of university research, is being increasingly guided by technology roadmaps. To a great extent, roadmaps also define the technologies that will be important to future college graduates-at least for the next 5-10 years. Thus, in a sense, they can also be a curriculum aid, in that certain trends and paradigm shifts are identified in the roadmapping activity. Graduate education in electronic packaging per se, can draw heavily on current roadmaps. This paper will describe the process by which the NEMI roadmap was developed; some of the effects the roadmap has already had on government agencies and research priorities; and how it can fruitfully be used to further identify potential curriculums for electronics packaging education.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A new family of ferruleless fiber-optic transceivers 一种新型无箍光纤收发器

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678693

J. Guenter, Phillip Waltrip, J. Tatum

{"title":"A new family of ferruleless fiber-optic transceivers","authors":"J. Guenter, Phillip Waltrip, J. Tatum","doi":"10.1109/ECTC.1998.678693","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678693","url":null,"abstract":"The historical inability of fiber-optic transmitters and receivers to equal the linear port density achieved by wire connectors has presented an obstacle to the widespread adoption of fiber in data communications networks. We have developed a family of fiber-optic transceiver modules spanning data rates from 10 to 1250 MB and employing the VF-45 duplex connector format (also known as the SG connector) which affords ferruleless fiber connections in a space similar to that occupied by RJ-45 wire connectors. Optical and electrical performance equals or exceeds that of typical ferruled-connector schemes. The optics employed in the transceivers vary depending on source characteristics and alignment requirements but share two features: a minimized number of optical interfaces and one-piece construction combining optical and mechanical elements. The electronics also vary depending on the functionality partitioning prevailing at each speed of operation, but share similar interconnection and fabrication schemes. The design was chosen to minimize functional problems that might be inherent in this miniaturization effort, including coupling variability and optical and electrical crosstalk. Extensive testing has demonstrated that these goals were achieved and surpassed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128920036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An innovative technique for packaging power electronic building blocks using metal posts interconnected parallel plate structures 利用金属柱相互连接的平行板结构包装电力电子积木的创新技术

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678819

S. Haque, K. Xing, R. Lin, C. Suchicital, G. Lu, Dennis P. Nelson, D. Borojevic, F. Lee

{"title":"An innovative technique for packaging power electronic building blocks using metal posts interconnected parallel plate structures","authors":"S. Haque, K. Xing, R. Lin, C. Suchicital, G. Lu, Dennis P. Nelson, D. Borojevic, F. Lee","doi":"10.1109/ECTC.1998.678819","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678819","url":null,"abstract":"Power Electronics Building Blocks (PEBBs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. At Virginia Power Electronics Center (VPEC), we developed a topology for a basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability. Based on the topology, a series of prototype modules, with 600 V, 3.3 kW rating, were fabricated using an innovative packaging technique developed for the program-metal posts interconnected parallel plate structure (MPIPPS). This new packaging technique uses direct attachment of bulk copper, not wire-bonding of fine aluminum wires, for interconnecting power devices. Electrical performance data of the packaged devices show that an air-cooled 15 kW inverter, operating from 400 V dc bus with 20 kHz switching frequency can be constructed by integrating three prototype modules, which is almost double of what could not be achieved with commercially packaged devices of the same rating.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128921801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 83

Thin film resistors and capacitors for multichip modules 多芯片模块用薄膜电阻器和电容器

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678698

A. Trigg, N. K. Keong, Ng Sok Fang, Liu Jun, L. Yan

{"title":"Thin film resistors and capacitors for multichip modules","authors":"A. Trigg, N. K. Keong, Ng Sok Fang, Liu Jun, L. Yan","doi":"10.1109/ECTC.1998.678698","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678698","url":null,"abstract":"A significant advantage of using thin film, rather than laminate technology, for MCMs is the ability to incorporate passive components, resistors, capacitors and spiral inductors at low cost. Tantalum-silicon alloy resistors and silicon nitride capacitors have been widely used but modifications to traditional processing have greatly improved the robustness of the process. The use of NF/sub 3/ gas for tantalum silicide etching provides excellent sidewall geometry and uniformity over the whole of the wafer so that narrow lines can yield high-tolerance resistors. It also fulfils the requirements of the Montreal Convention. Silicon nitride capacitors are formed using plasma enhanced chemical vapour deposition (PECVD) instead of low pressure chemical vapour deposition so as to reduce the temperature of deposition from 785/spl deg/C to 400/spl deg/C. This minimises oxidation of the tantalum silicide and the associated resistor drift. The PECVD nitride provides pinhole free capacitors with a yield of >99% up to 3 mm square. Breakdown strength is in excess of 1.7/spl times/10/sup -6/ V/cm. PECVD also provides excellent uniformity, <2% over a 150 mm wafer. The values of resistors fall by 5% during polyimide cure at 400/spl deg/C but there is no widening of the distribution so the tolerance is not affected. The thermal coefficient of resistance is less than 100 ppm/K over the temperature range 25-175/spl deg/C.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128983695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Stencil printing process development for low cost flip chip interconnect 低成本倒装芯片互连的模板印刷工艺开发

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678728

Li Li, S. Wiegele, P. Thompson, R. Lee

{"title":"Stencil printing process development for low cost flip chip interconnect","authors":"Li Li, S. Wiegele, P. Thompson, R. Lee","doi":"10.1109/ECTC.1998.678728","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678728","url":null,"abstract":"Traditional methods for forming flip chip interconnection include evaporation and electroplating. While both options have proven performance records, their costs are too high for many of today's cost-sensitive applications. Motorola AISL (Advanced Interconnect Systems Laboratory) developed a low cost flip chip interconnect alternative, which electroless plates Ni/Au as the under bump metallurgy (UBM), deposits solder paste using a stencil or photoresist mask, and reflows the paste to form solder bumps. This paper is focused on the stencil print process development for wafer solder bumping. Solder paste selection, characterization, stencil design, and process parameter optimization are critical factors for successful fine pitch stencil printing. Fine mesh eutectic solder pastes (Type 5: -500+635, Type 6: -635) with different flux vehicles were evaluated for printability and reflow studies. Paste and flux modification and co-development with vendors for this specific application were conducted. An optimal paste, with specified viscosity and desired print, reflow and cleaning behavior, was developed. Wafer stencil design rules were established to deposit the right amount of solder paste to form the required reflowed solder bump height without bridges between pads. Printing and reflow design of experiments were performed to establish the baseline and optimum process parameters. Solder bump characterizations, including bump height and uniformity, composition, shear force, and SEM bump profile and cross section microstructure analysis, were conducted. Development and characterization results are presented.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129156612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Transient heat conduction analysis of electronic packages by coupled boundary and finite element methods 电子封装瞬态热传导的耦合边界与有限元分析

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678671

I. Guven, E. Madenci, C. Chan

{"title":"Transient heat conduction analysis of electronic packages by coupled boundary and finite element methods","authors":"I. Guven, E. Madenci, C. Chan","doi":"10.1109/ECTC.1998.678671","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678671","url":null,"abstract":"Electronic packages experience large temperature excursions during their fabrication and under operational conditions. Inherent to electronic packages are the presence of geometric and material discontinuities. The regions where adhesive bond lines intersect with convective heat loss surfaces are the most critical locations for failure initiation due to heat flux singularities and extreme thermo-mechanical stresses. Thus, accurate calculation of the flux field, as well as the temperature field, is essential in transient thermomechanical stress analysis. Although the finite element method (FEM) is highly efficient and commonly used, its application with conventional elements suffers from poor accuracy in the prediction of the flux field in these regions. The accuracy of the results from the boundary element method (BEM) formulation, which requires computationally intensive time-integration schemes, is much higher than that of the FEM. However, in this study, a novel boundary element-finite element coupling algorithm is developed to investigate transient thermal response of electronic packages consisting of dissimilar materials. The new algorithm combines the advantages of both methods while not requiring any iterations along the interfaces between BEM and FEM domains.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"62 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130648439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Three dimensional die surface stress measurements in delaminated and non-delaminated plastic packages 在脱层和非脱层塑料包装中的三维模具表面应力测量

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678885

Y. Zou, J. Suhling, R. Jaeger, H. Ali

{"title":"Three dimensional die surface stress measurements in delaminated and non-delaminated plastic packages","authors":"Y. Zou, J. Suhling, R. Jaeger, H. Ali","doi":"10.1109/ECTC.1998.678885","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678885","url":null,"abstract":"In plastic encapsulated electronic packages, mechanical stresses are induced during the encapsulation process. These stresses can cause degraded circuit performance or mechanical failures, and are mainly a result of the uneven expansions and contractions of the various assembly materials that occur due to coefficient of thermal expansion (CTE) mismatches. In this study, special (100) and (111) silicon test chips containing arrays of optimized piezoresistive stress sensor rosettes have been used to characterize die surface stresses in encapsulated packages. The sensors on the (100) test chips were able to accurately measure two in-plane stress components in a temperature compensated manner, while the rosettes on the (111) test chips were uniquely capable of evaluating all the 6 stress components (four in a temperature compensated manner). Calibrated and characterized (100) and (111) test chips were encapsulated in 240 pin quad flat packs (QFP's). The post packaging room temperature resistances of the sensors were then recorded. The stresses on the die surface were calculated using the measured resistance changes and the appropriate theoretical equations. For comparison purposes, three-dimensional nonlinear finite element simulations of the plastic encapsulated packages were also performed. The presence of delaminations between the die surface and the encapsulant was explored using C-mode scanning acoustic microscopy (C-SAM). The potential of the (111) stress test chips for detecting delaminations and for aiding the understanding of stress distributions in delaminated packages has been demonstrated.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132519660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Thermo-mechanical creep of two solder alloys 两种焊料合金的热-机械蠕变

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678932

W. Ren, Z. Qian, Sheng Liu

引用次数: 13