1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献_第4页

An analytical characterization and reliability testing of an adhesion enhancing Zn-Cr leadframe coating for popcorn prevention 一种防爆用增粘锌铬引线骨架涂层的分析表征及可靠性试验

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678862

C. Lee, W. Hosler, H. Cerva, R. von Criegern, A. Parthasarathi

{"title":"An analytical characterization and reliability testing of an adhesion enhancing Zn-Cr leadframe coating for popcorn prevention","authors":"C. Lee, W. Hosler, H. Cerva, R. von Criegern, A. Parthasarathi","doi":"10.1109/ECTC.1998.678862","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678862","url":null,"abstract":"A novel Zn-Cr (A2) leadframe coating has been developed and demonstrated to be an effective solution in eliminating popcorn cracking. In this investigation, the A2-coating structure and molding compound (MC)/Cu leadframe (LF) interface was analyzed by Transmission Electron Microscopy (TEM) and Time-of-Flight Secondary Ion Mass Spectrometry (TOF-SIMS). The A2-coating was found to be a thin, partly crystalline layer comprising a continuous interfacial layer and a network of whiskers. The TOF-SIMS and TEM results have identified Zn silicate compound, ZnO and Cr oxide(s) as possible phases present in the coating. The effect of temperature cycling, pressure cooker testing, moisture pre-conditioning, and overheating on the A2 adhesion and degradation mechanism was investigated using a lead pull test. The adhesion data showed that the A2-enhanced MC/Cu LF adhesion is resistant to thermomechanical stress and moisture degradation. The wetting of the molding compound and mechanical interlocking offered by the whiskers are believed to be key factors of adhesion enhancement. Degradation of the A2-enhanced MC/Cu LF adhesion was observed at 300/spl deg/C after 100 mins exposure through Cu oxide formation by Cu outward diffusion. This was verified by Auger Electron Spectroscopy (AES) analysis operated in the depth profiling mode. Lead pull test specimens were mechanical cleaved to have access to the MC/Cu LF interface for Rutherford Backscattering Spectroscopy (RBS) analysis to identify the locus of failure for various samples.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125304045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Termination of small diameter (125 /spl mu/m) plastic optical fiber for 1/spl times/12 datacommunication 端接小直径(125 /spl mu/m)塑料光纤进行1/spl次/12次数据通信

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678796

A. Van Hove, T. Coosemans, B. Dhoedt, P. van Daele, R. Baets, J. Van Koetsem, L. van den Torren

引用次数: 0

Resolving displacement field of solder ball in flip-chip package by both phase shifting moire interferometry and FEM modeling 用相移云纹干涉法和有限元模拟相结合的方法求解倒装封装中焊球的位移场

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678919

Sheng Liu, Jianjun Wang, D. Zou, Xiaoynan He, Z. Qian, Yifan Guo

{"title":"Resolving displacement field of solder ball in flip-chip package by both phase shifting moire interferometry and FEM modeling","authors":"Sheng Liu, Jianjun Wang, D. Zou, Xiaoynan He, Z. Qian, Yifan Guo","doi":"10.1109/ECTC.1998.678919","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678919","url":null,"abstract":"In this paper, phase shifting moire interferometry was used to resolve the deformation field of solder balls in a flip-chip package under thermal loading condition. A nanoscale deformation field of the outmost solder ball was obtained by using the proposed phase shifting technique associated with the corresponding image processing software. In addition, a nonlinear finite element technique, in which the viscoelastic material properties of underfill and the viscoplastic material properties of solder balls were considered was also adapted to simulate the global displacement field - the whole cross-section of the flip-chip package and the local displacement field - the whole cross-section of one solder ball in the flip-chip package. By comparing the predicted deformation values of the flip-chip package obtained from the finite element analysis with the test data obtained from the laser moire interferometry technique, good agreement is obtained. In particular, the nanoscale displacement contours of the solder ball both in x and y directions obtained from the phase shifting technique show much more similar distribution patterns compared with those modeled by the finite element method.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122946773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Flip-chip bonding on 6-/spl mu/m pitch using thin-film microspring technology 利用薄膜微弹簧技术在6-/spl μ m间距上进行倒装键合

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678714

D.L. Smith, D. Fork, R. Thornton, A. Alimonda, C. Chua, C. Dunnrowicz, J. Ho

引用次数: 28

On thermal stresses and reliability of a PBGA chip scale package PBGA芯片级封装的热应力与可靠性研究

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678740

B. Z. Hong, L. Su

{"title":"On thermal stresses and reliability of a PBGA chip scale package","authors":"B. Z. Hong, L. Su","doi":"10.1109/ECTC.1998.678740","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678740","url":null,"abstract":"Thermomechanical analysis using the nonlinear finite element method was performed to study the thermal stresses and reliability problems of a flip chip plastic ball grid array (PBGA) chip scale package (CSP). The package under investigation has the fully populated PBGA solder joints in an array pitch of 1.27 mm. A cyclic temperature load of 0-100/spl deg/C at a frequency of 2 cycles per hour was applied to the modeled package. The dependence of solder joint reliability on the CSP configuration and the use of mold compound was demonstrated for various chip sizes varying from 5 mm to 20 mm. The analysis results show that the chip-outline solder joint may fail earlier than any other solder joint in the modeled package. This confirms both experimental and modeling observations in the literature that the interior PBGA solder joint failure is mainly caused by the thermally induced warpage of organic-based package. It is contrary to the classical DNP theory used in predicting the fatigue failure location and mechanism of solder joints in the ceramic-based packages. The overmold flip chip PBGA chip scale package has a mean thermal fatigue life of the first failed solder joint that is approximately 1.2/spl times/ that of the standard flip chip PBGA scale package without overmold.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125192512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Compression flow modeling of underfill encapsulants for low cost flip chip assembly 用于低成本倒装芯片组装的下填充封装料的压缩流建模

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678735

N. W. Pascarella, D. Baldwin

{"title":"Compression flow modeling of underfill encapsulants for low cost flip chip assembly","authors":"N. W. Pascarella, D. Baldwin","doi":"10.1109/ECTC.1998.678735","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678735","url":null,"abstract":"Currently, underfill dispense processing is achieved through capillary action, making it a costly and time consuming process. As part of the Low Cost Next Generation Flip Chip Processing Program at Georgia Tech, an advanced flip chip assembly process was developed. This process eliminated the need for time consuming capillary flow processing, and integrates the simultaneous reflow and cure of the solder interconnect and polymer underfill. The advanced process results in a significantly lower assembly cost combined with reduced throughput time. Reduced throughput time and cost were achieved through the compression flow of the underfill material. The flow of the material governs assembly yield and reliability. Flow simulation studies of the placement process were conducted to characterize the compression flow of the underfill and predict void formation. Results yielded design guidelines that gave insight into process parameters such as the limits on underfill print height and underfill viscosity. The results indicated the initial limits of an overall process window for compression flow chip placement.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Flip chip for AMD K6 microprocessor 倒装芯片为AMD K6微处理器

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678711

R. Master, M. Khan, Martin Guardado, O. Starr, E. Alcid, L. Khor

{"title":"Flip chip for AMD K6 microprocessor","authors":"R. Master, M. Khan, Martin Guardado, O. Starr, E. Alcid, L. Khor","doi":"10.1109/ECTC.1998.678711","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678711","url":null,"abstract":"Flip-chip technology in the form of Controlled Collapse Connection (C4) was adopted for the AMD K6 microprocessor. The need arose from the pad limitations of wire-bond technology. The necessity of more pads for connectivity resulted in growth of die size. This would have impacted the net die per wafer and, therefore, the capacity of the wafer fabrication facilities. In addition, flip-chip technology afforded increased electrical performance. The paper describes the various materials/processes that were developed and qualified for manufacturing. The paper presents improvement to various traditional processes of flux application, flux cleaning, and underfill. The criterion used for the material and process development is described. In addition, reliability data are presented for two assembly sites, one in the US and the other in Malaysia. The data includes accelerated thermal cycles at two different conditions, and various underfill materials and cleaning methods. Also presented are the improvement to solder joint reliability due to use of underfill. In this particular application, it turned out to be at least 50X. The Malaysian facility is the first outside the United States to practice flip-chip technology in high-volume manufacturing for microprocessor application. This presented significant challenges in developing both equipment and support infrastructure. The paper concludes with a typical line layout of a high volume manufacturing line.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127588748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Electrical evaluation of flip-chip package alternatives for next generation microprocessors 下一代微处理器倒装封装替代方案的电气评估

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678769

J. Darnauer, D. Chengson, B. Schmidt, E. Priest, B. Petefish, D. Hanson, W. L. Gore

引用次数: 18

Tacky Dots/sup TM/ transfer of solder spheres for flip chip and electronic package applications 用于倒装芯片和电子封装应用的粘点/sup TM/焊球转移

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678730

G. Hotchkiss, G. Amador, L. Jacobs, R. Stierman, S. Dunford, P. Hundt, A. Beikmohamadi, A. Cairncross, O. Gantzhorn, B. Quinn, M. Saltzberg

{"title":"Tacky Dots/sup TM/ transfer of solder spheres for flip chip and electronic package applications","authors":"G. Hotchkiss, G. Amador, L. Jacobs, R. Stierman, S. Dunford, P. Hundt, A. Beikmohamadi, A. Cairncross, O. Gantzhorn, B. Quinn, M. Saltzberg","doi":"10.1109/ECTC.1998.678730","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678730","url":null,"abstract":"The use of preformed solder spheres for bumping flip chip wafers has not gained wide acceptance within the semiconductor industry. Due in part to equipment shortcomings, solder sphere transfer until now was commonly limited to spheres 300 /spl mu/m or larger, much too large for the typical flip chip applications of 150 /spl mu/m or less. To address this need, Texas Instruments and DuPontB have jointly developed a process for transferring 127 /spl mu/m diameter solder spheres to wafers. The process, called Tacky Dots/sup TM/, forms are array of sticky or tacky dots in a photoimageable adhesive coating. Solder spheres sprinkled on the adhesive coating are then captured and retained by the tacky dots until the spheres are aligned and reflowed to the wafer. This paper describes the equipment and processes developed for bumping wafers using Tacky Dots/sup TM/. The compliant polyimide sheet used in Tacky Dots/sup TM/ required a new and unique equipment design that aligns the solder spheres to the wafer and then reflows the solder without moving the wafer. Post reflow analysis of the bumped dies before and after environmental testing is reviewed. Tests conducted with a leadless chip carrier package design are also reviewed to demonstrate the capability of Tacky Dots/sup TM/ at transferring spheres to electronic packages and substrates other than wafers.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132643053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Thermal simulation and validation of the fast static RAM 164-lead FC-PBGA package with investigations of package thermal performance in a generic CPU module 快速静态RAM 164导联FC-PBGA封装的热模拟与验证，并研究了封装在通用CPU模块中的热性能

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678672

M. Eyman, Z. Johnson, B. Joiner

{"title":"Thermal simulation and validation of the fast static RAM 164-lead FC-PBGA package with investigations of package thermal performance in a generic CPU module","authors":"M. Eyman, Z. Johnson, B. Joiner","doi":"10.1109/ECTC.1998.678672","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678672","url":null,"abstract":"The steady-state thermal performance of the 164-lead flip chip plastic ball grid array (FC-PBGA) under low to moderate convective air cooling conditions has been simulated through finite element (FE) methods and computational fluid dynamics (CFD) methods. Experimental measurements taken with thermal test vehicles of this package were used to validate the simulations. Packages with three different substrates were investigated. Package performance has been presented in the form of a linear relationship between the normalized junction-to-ambient thermal resistance (/spl theta//sub JA/) versus the normalized board-to-ambient thermal parameter (/spl psi//sub BA/). Results cast in this form represent a first-order thermal figure of merit for packages. Such a figure of merit can be used to rank in a consistent manner the thermal performance of different package types. A CFD study was performed to investigate the thermal performance of the package on a central processing unit (CPU) module assembly. A parametric study was performed to investigate the die temperatures as a function of thermal interface materials and heat sink configuration. Sink solutions were studied. The results of those board-level simulations give a reasonable indication of how the package would perform in a workstation environment.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132132391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6